Characterizing the impact of different memory-intensity levels

Abstract

Applications on today's high-end processors typically make varying load demands over time. A single application may have many different phases during its lifetime. and workload mixes show interleaved phases. This work examines and uses the differences between mentoyv-and CPU-intensive phi1sc.v to reduce power. Today's processors provide rt'sou~'ces that are underut ilized during memoryintensive phases, consuming power while producing little incremental gain in performance. This work examines a deployed system consisting of identical cores with a goat of running each one at a different effective frequency. The initial goal is to find the appropriate frequency at which to run each phase.This paper denionstrates that memory intensity directly affects the throughput of applications. The results indicate that siniple metrics such as IPC (instructions per cycle) cannot be used to determine what fi-equency to run R phase. Instead, it uses performance counters which directly monitor memory behavior to identify. Memory-intensive phases can then be run on a slower core without incurring significant performance penalties. The key result of the paper is the introduction o f a very simple, online model that uses the perforniance counter data to predict rhe perforniance of a program phase at any particular frequency setting. The information from this model allows a scheduler to decide which core to use to execute the program phase. Using a sophisticated power model for the processor family shows that this approach significantly reduces power consumption. The model was evaluated using a subset of SPECCPU and the SPECjbb and TPC-W benchmarks. It predicts perforinance with an average error of less than 10%. The power modeling shows that memory-intensive benchmarks achieve up to a 58% power reduction at a performance loss o f less than 20% when run at 80% of nominal frequency.

Dynamic Scheduling for Energy Minimization in Delay-Sensitive Stream Mining

“…Note that even though the processing nodes are physically the same, the processing speed set may still be dependent on classification stages [23]. For notational convenience, we use the vectorial expression wherever applicable.…”

“…For stage , we relate the processing speed to energy consumption via an energy function . Here, we explicitly include the subscript in the energy function to emphasize that the energy consumption may be different even though two different stages and are executed using the same physical hardware at the same speed, because each stage may involve different types of classification operations that exhibit different power-performance characteristics [4], [23]. Without loss of generality, we consider that a faster node incurs more energy for a given classification stage, i.e., is increasing in , since otherwise the problem becomes trivial: a slower node will not be used due to its lower performance and higher energy consumption.…”

“…The subscript in is to emphasize that the same processing node may exhibit different speeds on different classifiers [23].…”

A Theoretical Foundation for Scheduling and Designing Heterogeneous Processors for Interactive Applications

“…Given a particular application, the effective speed x and power z(x) can be obtained by system measurements. Consequently, the effective speed x may differ from the clock rate of CPU and both clock speed an power may vary depending on the application [14,20].…”

Beyond CPU Frequency Scaling for a Fine-grained Energy Control of HPC Systems

“…Our approach differs from that implemented in Adagio in that our fine-grained data collection gives the possibility to differentiate not only computation-intensive and communication-intensive execution portions (which we call phases/regions), but also memory-intensive portions. Memory-intensive phases can be run on a slower core without significant performance penalty [4]. They also differ in that we consider different green leverages, not only DVFS.…”