Characterizing a Heterogeneous System for Person Detection in Video Using Histograms of Oriented Gradients: Power Versus Speed Versus Accuracy

Blair, Calum G.; Robertson, Neil; Hume, Danny

doi:10.1109/jetcas.2013.2256821

Cited by 25 publications

(25 citation statements)

References 27 publications

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“…The reported maximum clock frequency is 127.49 MHz but with a maximum frame rate of 30 fps at VGA resolution. Another heterogeneous HOG architecture has been proposed in [4]. But, due to the processing bottleneck caused by the PCIe communication interface between the FPGA and the rest of the system, the histogram computation is 10x time slower than in our solution (657 µs instead of 64.4 µs).…”

Section: Performance Evaluationmentioning

confidence: 87%

“…Typically, design proceeds by moving computationally intensive parts of the application from software to hardware accelerators, while keeping in software the parts having the lowest computational cost and/or the more demanding requirement in terms of arithmetic precision. In [19,1,4] several methods, aiming at finding the "best" partition between the hardware and software parts, have been formally analysed to distinguish their benefits in terms of development time, efficiency and architecture optimisation. The approach we propose and describe in Sec.…”

Section: Related Workmentioning

confidence: 99%

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Bio-inspired heterogeneous architecture for real-time pedestrian detection applications

Maggiani

Bourrasset

Quinton

et al. 2016

J Real-Time Image Proc

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International audienceAlong with the development of powerful processing platforms, heterogeneous architectures are nowadays permitting new design space explorations. In this paper we propose a novel heterogeneous architecture for reliable pedestrian detection applications. It deploys an efficient Histogram of Oriented Gradient pipeline tightly coupled with a neuro-inspired spatio-temporal filter. By relying on hardware-software co-design principles, our architecture is capable of processing video sequences from real-word dynamic environments in real-time. The paper presents the implemented algorithm and details the proposed architecture for executing it, exposing in particular the partitioning decisions made to meet the required performance. A prototype implementation is described and the results obtained are discussed with respect to other state of the art solutions

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Section: Performance Evaluationmentioning

confidence: 87%

Section: Related Workmentioning

confidence: 99%

Bio-inspired heterogeneous architecture for real-time pedestrian detection applications

Maggiani

Bourrasset

Quinton

et al. 2016

J Real-Time Image Proc

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show abstract

“…A detailed description of HOG implementation on FPGA is presented in [9], which achieves a high processing speed at 40 fps, with 1920 × 1080 input image size. Interestingly, in [10], HOG algorithm is analyzed on a heterogeneous system, including CPU, GPU, and FPGA. Based on multiple configuration experiments, the authors concluded that FPGA is best suited for histogram extraction and classification tasks in the whole detection flow because it produces a good trade-off between power and speed.…”

Section: Related Workmentioning

confidence: 99%

Low-Power Pedestrian Detection System on FPGA

Ngo

Castells-Rufas

Casadevall

et al. 2019

13th International Conference on Ubiquitous Computing and Ambient ‪Intelligence UCAmI 2019‬

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Pedestrian detection is one of the key problems in the emerging self-driving car industry. In addition, the Histogram of Gradients (HOG) algorithm proved to provide good accuracy for pedestrian detection. Many research works focused on accelerating HOG algorithm on FPGA (Field-Programmable Gate Array) due to its low-power and high-throughput characteristics. In this paper, we present an energy-efficient HOG-based implementation for pedestrian detection system on a low-cost FPGA system-on-chip platform. The hardware accelerator implements the HOG computation and the Support Vector Machine classifier, the rest of the algorithm is mapped to software in the embedded processor. The hardware runs at 50 Mhz (lower frequency than previous works), thus achieving the best pixels processed per clock and the lower power design.

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“…Because of deeply pipelined architectures and lower power consumption, FPGA platforms often provide higher execution speed and better energy efficiency over GPUs [16]. An FPGA-GPU hybrid system was proposed in [17] using FPGA to extract HOG features and GPU to perform classification; it achieved a throughput of 10,000 detection windows per second for FPGA execution.…”

Section: Background a Related Workmentioning

confidence: 99%

“…Our experiments have shown that a scale factor 1.2 has 3.25x less computation than the 1.05 scale factor used in this paper and 6x poorer detection accuracy, in terms of true positives. In [16] a person detection execution on CPU, GPU and FPGA was compared for power, speed and accuracy. The FPGA implementation focused only on 4 out of 37 scales for 640×480 images and achieves 30 fps.…”

Section: Background a Related Workmentioning

confidence: 99%

Evaluation and Acceleration of High-Throughput Fixed-Point Object Detection on FPGAs

Najjar

Roy-Chowdhury

2015

IEEE Trans. Circuits Syst. Video Technol.

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Abstract-The reliance on object or people detection is rapidly growing beyond surveillance to industrial and social applications. The Histogram of Oriented Gradients (HOG), one of the most popular object detection algorithms, achieves high detection accuracy but delivers just under one frame-per-second (fps) on a high-end CPU. FPGA accelerations of this algorithm are limited by the intensive floating-point computations. All current fixedpoint HOG implementations use large bit-width to maintain detection accuracy, or perform poorly at reduced data precision. In this paper we introduce the full-image evaluation methodology to explore the FPGA implementation of HOG using reduced bit-width. This approach lessens the required area resources on the FPGA and increases the clock frequency and hence the throughput per device through increased parallelism. We evaluate the detection accuracy of the fixed-point HOG by applying state-of-the-art computer vision pedestrian detection evaluation metrics and show it performs as well as the original floatingpoint code from OpenCV. We then show our single FPGA implementation achieves a 68.7x higher throughput than a highend CPU, 5.1x higher than a high-end GPU, and 7.8x higher than the same implementation using floating-point on the same FPGA. A power consumption comparison for different platforms shows our fixed-point FPGA implementation uses 130x less power than CPU, and 31x less energy than GPU to process one image.

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Characterizing a Heterogeneous System for Person Detection in Video Using Histograms of Oriented Gradients: Power Versus Speed Versus Accuracy

Cited by 25 publications

References 27 publications

Bio-inspired heterogeneous architecture for real-time pedestrian detection applications

Bio-inspired heterogeneous architecture for real-time pedestrian detection applications

Low-Power Pedestrian Detection System on FPGA

Evaluation and Acceleration of High-Throughput Fixed-Point Object Detection on FPGAs

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