Characterization of wafer geometry and overlay error on silicon wafers with nonuniform stress

Abstract

Abstract. Process-induced overlay errors are a growing problem in meeting the ever-tightening overlay requirements for integrated circuit production. Although uniform process-induced stress is easily corrected, nonuniform stress across the wafer is much more problematic, often resulting in noncorrectable overlay errors. Measurements of the wafer geometry of free, unchucked wafers give a powerful method for characterization of such nonuniform stress-induced wafer distortions. Wafer geometry data can be related to in-plane distortion of the wafer pulled flat by an exposure tool vacuum chuck, which in turn relates to overlay error. This paper will explore the relationship between wafer geometry and overlay error by the use of silicon test wafers with deliberate stress variations, i.e., engineered stress monitor (ESM) wafers. A process will be described that allows the creation of ESM wafers with nonuniform stress and includes many thousands of overlay targets for a detailed characterization of each wafer. Because the spatial character of the stress variation is easily changed, ESM wafers constitute a versatile platform for exploring nonuniform stress. We have fabricated ESM wafers of several different types, e.g., wafers where the center area has much higher stress than the outside area. Wafer geometry is measured with an optical metrology tool. After fabrication of the ESM wafers including alignment marks and first level overlay targets etched into the wafer, we expose a second level resist pattern designed to overlay with the etched targets. After resist patterning, relative overlay error is measured using standard optical methods. An innovative metric from the wafer geometry measurements is able to predict the process-induced overlay error. We conclude that appropriate wafer geometry measurements of in-process wafers have strong potential to characterize and reduce process-induced overlay errors.

Dielectric Barrier, Etch Stop, and Metal Capping Materials for State of the Art and beyond Metal Interconnects

“…50.77 The compressive stresses are useful for counteracting the tensile stresses present in the low-k ILD from both a mechanical reliability perspective and from a more mundane wafer curvature perspective where overly bowed wafers can create wafer pick-up, chucking, and registration issues on manufacturing tools. 186 However, there are limitations to the amount of desirable compressive stress in a low-k DB material. At sufficiently high stresses, mechanical failure can also occur for a compressive film via out of plane buckling of the DB.…”

Monitoring process-induced overlay errors through high-resolution wafer geometry measurements

“…Overlay budgets in many processes are in the sub-10 nm regime today and are expected to shrink to 3 nm by 2016 [1,2]. Overlay errors can result from multiple sources including the exposure tool, reticle, and wafer processing.…”

“…This has changed as overlay error budgets have been reduced to the sub-10 nm regime. Several papers examining aspects of process induced overlay errors have been published in the past 5 years (e.g., [2,4,5]). In 2012, our team demonstrated that if a deposited film has a uniform residual stress that does not vary with location on the wafer then the induced distortions can be fully compensated for through the application of standard linear corrections in the scanner [5].…”

“…The residual shape map provides a simple wafer-level measure of the stress non-uniformity [5]. A collaborative effort between IBM and KLA-Tencor experimentally examined relationships between wafer geometry and overlay errors in 2013 [2]. Wafer geometry and overlay were characterized on engineered stress monitor (ESM) wafers that were fabricated to have specific stress distributions via the deposition of a residually stressed nitride film and subsequent patterning and etching.…”

Effects of Anisotropy and Supporting Configuration on Silicon Wafer Profile Measurements for Pattern Overlay Estimation

“…4,5 The monitoring and control of process induced wafer geometry change (PIWGC) is critical to achieving high device yield in advanced semiconductor manufacturing processes such as lithography, chemical mechanical polishing (CMP) and wafer bonding processes. [3][4][5][6][7][8][9][10][11][12] Conventional wafer supporting methods (3-or 4-point supports) are less suitable for flatness characterization of large diameter wafers due to effects of gravity. 4 Adverse effects of 3-point support methods and anisotropy on shape measurement accuracy was reported in detail.…”