Characterization of various low-kdielectrics for possible use in applications at temperatures below 160 °C

Photo-patternable fluorinated polyhedral oligomeric silsequioxane-functionalized (POSS-F) polymeric materials with ultra low dielectric constants

“…The influence of POSS substituents on the lithographic characteristics of the resist has been reported previously [25,26]. In addition, it has been shown that silsesquioxane cage groups demonstrate reduced k values because of the decreased material's density, which derives from the way that Si and O atoms are arranged in the silsesquioxane elementary unit [17,27]. The second component is t-butyl methacrylate (TBMA) that provides the acid-labile tert-butyl group, necessary for the photoinduced solubility change.…”

“…In our previous work POSS-F copolymers containing CeF bonds and silsesquioxane cage groups were characterised and found materials with reduced k values because of the decreased material's density, which derives from the way that Si and O atoms are arranged in the silsesquioxane elementary unit [17]. POSS-F copolymers showed a considerably low dielectric constant with a value of about 2.5 (see Table 1).…”

“…Incorporation of a high percentage of CeC building blocks with low polarizability in the polymer backbone can decrease the dielectric constant [18e20]. In addition, lower density configurations correspond to lower density of components that contribute to the molecular polarizability [16,17]. Accordingly, another method that can be used to lower the dielectric constant is to lower the density of polymer films.…”

“…In our previous work polymeric materials based on partially fluorinated, polyhedral oligomeric silsesquioxane (POSS) functionalized (meth)acrylates (POSS-F) with low dielectric constant were presented [16,17]. These materials show low dielectric constant, because they contain a high percentage of the low polarizable SieO and CeF bonds, and therefore they are completely transparent in the visible light.…”

Analysis of Capacitance Across Interconnects of Low-K Dielectric Used in a Deep Sub-Micron Cmos Technology

“…At the same time, improvements in materials technology have allowed integration of more and more devices on the same chip, resulting in increased area. According to theory of scaling [3][4][5][6], the smaller dimensions of an MOS transistor should enhance its speed. The cause of gate delay increase is that drain current decreases at low supply voltages.…”