Characterization of the CMS Endcap Timing Layer readout chip prototype with charge injection

Sun, H.; Gong, D. T.; Zhang, W.; Edwards, C.; Huang, Chin-Hai; Huang, X.; Liu, C.; Liu, T.; Olsen, J.; Sun, Quan; Wu, Jia-Jun; Ye, J.; Zhang, L.

doi:10.1088/1748-0221/16/06/p06038

Cited by 11 publications

(9 citation statements)

References 17 publications

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“…During the research and development of the LGAD readout, some prototype ASICs have been designed and tested, such as ALTIROC [11,12] and ETROC [13,14], and the research is going on. During the development of both ALTIROC and ETROC, their first versions aim to study the performance of the analog front-end, without on chip TDC.…”

Section: Jinst 17 T09004mentioning

confidence: 99%

“…Usually there are two ways to achieve this requirement, using common gate structure (shown in figure 2(a)), e.g. like NINO ASIC [18], or common source structure with a feedback resistor (shown in figure 2(b)), like ALTIROC [11,12] and ETROC [13,14]. The former way, common gate structure, is able to keep a low input impedance in a wide bandwidth, so it is suitable to match the impedance of transmission line.…”

Section: Pre-amplifiermentioning

confidence: 99%

“…through bump bonding), so common source structure with a feedback resistor is preferred. The noise related leading edge jitter of the pre-amplifier out waveform has been analyzed in [13] and [14], which is:…”

Section: Pre-amplifiermentioning

confidence: 99%

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Design of a prototype analog front-end ASIC for the LGAD readout

et al. 2022

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Low-gain avalanche detector (LGAD) is being researched and designed in ATLAS and CMS experiments aiming to distinguish collisions that are close in both space and time to meet the challenge of pileup in HL-LHC, through its high resolution in position and time measurement. Considering the high spatial density of the detector channels, the area and power consumption per each channel are quite limited, so a front-end ASIC, instead of discrete-component electronics, is expected to collect and process the signal output by the LGAD. The processed signal is a digital pulse containing the precise information of time of arrival (TOA) and time over threshold (TOT). A prototype analog front-end ASIC for LGAD readout based on 180 nm CMOS technology with low power consumption, called LATIC0, has been designed and tested. As the first prototype, this ASIC aims to study the performance of the analog front-end for the further work. And the test results indicate that a time precision better than 20 ps-rms is achieved (at 10 fC injected charge with 6 pF capacitance), and the curves of TOA and TOT versus charge concord well with expectations.

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Section: Jinst 17 T09004mentioning

confidence: 99%

Section: Pre-amplifiermentioning

confidence: 99%

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Design of a prototype analog front-end ASIC for the LGAD readout

et al. 2022

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“…It is dominated by the preamplifier baseline and impacted by the input-referred offset voltage of the discriminator. The impact of the threshold on the performance was studied with SPICE simulation, where an LGAD signal set from WeightField2 [12] simulation with a large range of amplitudes was applied to input ETROC analog front-end [13,14]. The charge variation of the 1000 events in the signal set introduces a significant time walk because of Landau distribution, and TOT-based time walk correction was applied.…”

Section: Motivation Of the In-pixel Threshold Calibrationmentioning

confidence: 99%

In-pixel automatic threshold calibration for the CMS Endcap Timing Layer readout chip

Sun¹,

Gong²,

Edwards³

et al. 2021

J. Inst.

Self Cite

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We present the implementation and verification of an in-pixel automatic threshold calibration circuit for the CMS Endcap Timing Layer (ETL) in the High-Luminosity LHC upgrade. The discriminator threshold of the ETL readout chip (ETROC) needs to be calibrated regularly to mitigate the circuit baseline change. Traditional methods need a lot of communication through a slow control system hence are time-consuming. This paper describes an in-pixel automatic scheme with improvements in operating time and usability. In this scheme, a sample-accumulation circuit is used to measure the average discriminator output. A binary successive approximation and linear combination scan are applied to find the equivalent baseline. The actual calibration procedure has been first implemented in FPGA firmware and tested with the ETROC front-end prototype chip (ETROC0). The calibration circuit has been implemented with Triple Modular Redundancy (TMR) and verified with Single Event Effects (SEEs) simulation. A complete calibration process lasts 35 ms with a 40 MHz clock. In the worst case, the dynamic and static power consumption are estimated to be 300 μW and 10.4 μW, respectively. The circuit design, implemented in a 65 CMOS technology, will be integrated into ETROC2, the next iteration of the ETROC with a 16 × 16 pixel matrix.

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“…Additional quantities, such as the collected charge and the noise level, need to be evaluated, as they determine the final achievable performance. Considering the requirements of future front-end ASICs, for example [11], a signal charge above 8-10 fC helps achieving a time resolution σ t < 50 ps. In general, the higher the charge, the better the front-end ASIC performs.…”

Section: And Noisementioning

confidence: 99%

Optimization of the Gain Layer Design of Ultra-Fast Silicon Detectors

Siviero,

Arcidiacono,

Borghi

et al. 2021

Preprint

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The defining feature of Ultra-Fast Silicon Detectors (UFSD) is their gain layer design. In this paper, the performance of several types of gain layers, measured with a telescope instrumented with a 90 Sr β-source, are reported. The sensors measured are produced by Fondazione Bruno Kessler (FBK) and by Hamamatsu Photonics (HPK). The FBK sensors feature three different gain layer designs, with boron and carbon co-implantation, and three sensor thicknesses (35, 45, and 55 µm), while the HPK sensors have two different gain layer designs (not carbonated) and two thicknesses (45 and 80 µm).The design yielding the best results, both when new and irradiated, is an FBK 45 µm-thick sensor with a carbonated deep gain layer where the carbon and the boron implants are annealed concurrently with a low thermal load. Exploiting the variety of designs presented in these productions, several additional studies on the UFSD working principles have also been performed.

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Characterization of the CMS Endcap Timing Layer readout chip prototype with charge injection

Cited by 11 publications

References 17 publications

Design of a prototype analog front-end ASIC for the LGAD readout

Design of a prototype analog front-end ASIC for the LGAD readout

In-pixel automatic threshold calibration for the CMS Endcap Timing Layer readout chip

Optimization of the Gain Layer Design of Ultra-Fast Silicon Detectors

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