Characterization of SiO₂/4H-SiC Interface by Device Simulation and Temperature Dependence of On-Resistance of SiC MOSFET

Abstract

MOS interface traps are characterized by device simulation on the basis of temperature dependence of lateral MOS-TEG devices on the same Al-implanted p-type region as vertical device. The simulation shows fairly large Dit in SiO2/4H-SiC interface, corresponding to the suggested trap density inside the conduction band. Temperature dependence of on-resistance is explained by application of evaluated interface properties to calculation of current voltage properties of vertical DMOSFET.

On the simulation and analytical modeling of on-state DC characteristics of Silicon Carbide Double-implanted MOSFETs

“…Finally, Ref. [12] fits the measured data with simulated results in which different values of D it are used in sub-threshold, near threshold and over threshold regions and ignores surface roughness scattering in mobility model.…”

“…From this point of view, the parameters reported in various publications [6][7][8][9][10][11][12] on SiC MOSFETs have limited utility in simulation of DMOSFETs in SiC. For example, Ref.…”

“…SENTAURUS [5], for simulating the on-state characteristics of a SiC DMOSFET at elevated temperatures. As we point out, the parameters reported in literature [6][7][8][9][10][11][12] cannot be used directly for such device simulations. Fig.…”

Inverse Modeling of 4H-SiC Trench Gate MOSFETs Validated with Electrical and Physical Characterization

“…SiC/SiO2 interface state densities are also tuned to fit the subthreshold slope of the Vg-Id curves [7].…”