Characterization of on‐chip miniature multi‐layer spiral inductors for RFICs

Abstract

Several existing closed‐form equations for calculating DC inductance and resistance of single‐spiral inductors are examined at first, and the most accurate formula is chosen for characterizing the DC inductance of multi‐layer spiral inductors. The partial element equivalent circuit (PEEC) method is implemented for computing their frequency‐dependent (AC) resistance and inductance. To validate our calculated results, we designed and fabricated some multi‐layer spiral inductors using standard 0.18 μm CMOS technology. The on‐chip measurements are carried out so as to obtain two‐port S‐parameters of these inductors. Excellent agreements are obtained between the calculated and experimental results, which include DC and low‐frequency inductances of three‐, four‐, and fiver‐layer spiral inductors, respectively. © 2007 Wiley Periodicals, Inc. Microwave Opt Technol Lett 49: 2932–2936, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.22917

A Subcutaneous Biochip for Remote Monitoring of Human Metabolism: Packaging and Biocompatibility Assessment

“…To this end, we propose an implantable coil based on the multi-layer approach. Such strategy, already exploited in integrated circuits [27], [28], it is not yet commonly used on printed circuit boards (PCB). In a multi-layer coil, a spiral inductor is replicated on the two layers of different PCBs.…”