Characterization of Novel Polycrystalline Silicon Thin-Film Transistors with Long and Narrow Grains

Abstract

Excellent characteristics of polycrystalline silicon (poly-Si) thin-film transistors (TFTs) with long and narrow grains aligned one-dimension have been experimentally clarified for the first time. The field effect mobility and on-off transition slope of n-channel and p-channel devices were as high as 685 cm 2 V À1 s À1 and 190 mV/decade and 145 cm 2 V À1 s À1 and 104 mV/ decade, respectively. Fluctuations of characteristics were considerably reduced by widening the channel, and uniform characteristics were observed when there were approximately twenty long grains within the channel. These results were obtained when the TFT channel was formed within a region free from grain boundaries formed by head-on collision of laterally growing grains and seeds used to initiate lateral grain growth. Material properties are discussed from the viewpoint of device characteristics.

High Performance and Low power Monolithic Three-Dimensional Sub-50 nm Poly Si Thin film transistor (TFTs) Circuits

“…Note that the surface roughness is a critical issue after the laser crystallized poly-Si process, resulting in the blistering effect because of the residual interior hydrogen during the laser annealing. However, other factors such as a long laser pulse with high energy may trigger the melting process of materials, resulting in rough surface, and deteriorates carrier mobility because of the electron scattering 17 , 18 . Therefore, the chemical-mechanical planarization (CMP) process will be used to reduce the surface roughness.…”

“…However, the CMP process can compensate such effects by providing a flat and thin channel to avoid scattering effect and achieve well gate control capability, especially in small size devices, which explains steeper subthreshold swing, higher on currents and lower V th with better uniformity, especially in CMP 20 nm condition. Moreover, in the conventional TFTs structure, the presence of numerous long grains in the channel width with different crystal orientations may statistically reduce the mobility 18 . It is why the minimum of µ FE with the poor carrier mobility was found for the channel widths of 400 nm and 1 µm because of the comparable scale between the channel width and grain size.…”

Design of Ultra-High Performance Si TFTs

“…Further extensive effort will be needed to obtain an orientation-controlled large mono-crystalline grain. At the present, the use of a poly-Si film with a long and narrow grain structure could be a practical solution for suppressing fluctuations in device characteristics (3). Figure 6 shows the relationship between V T dispersion and channel width for 1 µm-long TFTs fabricated on a poly-Si film with long and narrow grains.…”

“…The maximum processing temperature was 600 °C during impurity activation. Details of the device fabrication process are reported elsewhere (3). The TFT channels are placed such that the current direction is parallel to the lateral growth direction.…”

Influence of annealing temperature and Au concentration on the electrical properties of multilayered a-Ge/Au films

“…To realize this, over the past few decades, low-temperature growth techniques of polySi and related alloys such as poly-SiGe on insulating substrate such as glass, plastic and polymer have been widely investigated [1][2][3][4][5]. The annealing technique using excimer laser is candidate for lowtemperature growth technique of poly-Si and related alloys from amorphous phase.…”