Characterization of high mobility inverted coplanar Zinc Nitride Thin-film Transistors

Abstract

In this work, high mobility TFTs based on zinc nitride (Zn3N2) sputtered at room temperature using spin-on glass (SOG) as gate dielectric are presented. The inverted coplanar structure is used for the Zn3N2 TFTs. The devices exhibit an on/off-current ratio of 106 and a subthreshold slope of 0.88 V/decade. The extracted field-effect mobility was 15.8 cm2/Vs which is among the highest reported for Zn3N2 TFTs. In addition, n-type MOS capacitors were fabricated and characterized by capacitance – voltage and capacitance – frequency measurements to evaluate the dielectric characteristics of the SOG film.

Low Residual Carrier Density and High In-Grain Mobility in Polycrystalline Zn3N2 Films on a Glass Substrate

“…The maximum μ sat = 46.6 cm 2 V −1 s −1 at V G = 1.1 V is derived from the transfer curve, which is close to the value of μ Hall,EDLT = 41.1 cm 2 V −1 s −1 measured with the same EDLT at a magnetic field of 2 T and V G of 1 V at T = 210 K. On the other hand, the D it of the present Zn 3 N 2 EDLT was high (5.2 × 10 13 eV −1 cm −2 ), which is much greater than D it of the reported Zn 3 N 2 TFT capped with ZnO layer (3.66 × 10 12 eV −1 cm −2 ) reported by Dominguez et al 27 If we consider a typical structure and operation condition of TFT (100 nm thick a-SiO 2 gate insulator and gate bias of 10 V), the maximum induced carrier density is 2.2 × 10 12 cm −2 , indicating that the large D it of Zn 3 N 2 EDLT must be reduced by more than an order of magnitude to fabricate a good Zn 3 N 2 TFT. The atomic force microscopy image in Figure S5 shows a rootmean-square roughness of 0.75 nm; however, the nonnegligible several grains (maximum ∼6.3 nm in peak-to-valley) can be seen, which causes carrier scattering in the channel of the top-gate EDLT.…”

“…I D reaches a minimum of ∼10 –10 A at approximately V G = −1 V, and the leakage gate current ( I G ) of the IL leads to increasing I D with higher negative V G < −1.4 V in the off region. In previous reports, the capacitance ( C i ) of the IL was reported as a function of the frequency and gate potential. , Here, we roughly estimate the saturation mobility (μ sat ) and interface state density ( D it ) of the EDLT assuming a gate capacitance of DEME-TFSI (2.7 μF cm –2 at 0.1 Hz) as follows: The maximum μ sat = 46.6 cm 2 V –1 s –1 at V G = 1.1 V is derived from the transfer curve, which is close to the value of μ Hall,EDLT = 41.1 cm 2 V –1 s –1 measured with the same EDLT at a magnetic field of 2 T and V G of 1 V at T = 210 K. On the other hand, the D it of the present Zn 3 N 2 EDLT was high (5.2 × 10 13 eV –1 cm –2 ), which is much greater than D it of the reported Zn 3 N 2 TFT capped with ZnO layer (3.66 × 10 12 eV –1 cm –2 ) reported by Dominguez et al If we consider a typical structure and operation condition of TFT (100 nm thick a-SiO 2 gate insulator and gate bias of 10 V), the maximum induced carrier density is 2.2 × 10 12 cm –2 , indicating that the large D it of Zn 3 N 2 EDLT must be reduced by more than an order of magnitude to fabricate a good Zn 3 N 2 TFT. The atomic force microscopy image in Figure S5 shows a root-mean-square roughness of 0.75 nm; however, the non-negligible several grains (maximum ∼6.3 nm in peak-to-valley) can be seen, which causes carrier scattering in the channel of the top-gate EDLT.…”