Characterization of data retention faults in DRAM devices

Bacchini, Angelo; Rovatti, Marco; Furano, Gianluca; Ottavi, Marco

doi:10.1109/dft.2014.6962069

Cited by 17 publications

(8 citation statements)

References 16 publications

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“…In turn, choosing an e ective test methodology requires knowledge of basic properties about a DRAM chip's design and/or error mechanisms 1 . For example, DRAM manufacturer's design choices for the sizes of internal storage arrays (i.e., mats [36,69,140,264]), charge encoding conventions of each cell (i.e., the true-and anti-cell organization [98,189]), use of on-die reliability-improving mechanisms (e.g., on-die ECC, TRR), and organization of row and column addresses all play key roles in determining if and how susceptible a DRAM chip is to key error mechanisms (e.g., data retention [95,98,189,191,[265][266][267], access-latency-related failures [37, 39,…”

Section: Information Flow During Testingmentioning

confidence: 99%

A Case for Transparent Reliability in DRAM Systems

Patel¹,

Shahroodi²,

Manglik³

et al. 2022

Preprint

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Mass-produced commodity DRAM is the preferred choice of main memory for a broad range of computing systems due to its favorable cost-per-bit. However, today's systems have diverse system-speci c needs (e.g., performance, energy, reliability) that are di cult to address using one-size-ts-all generalpurpose DRAM. Unfortunately, although system designers can theoretically adapt commodity DRAM chips to meet their particular design goals (e.g., by exploiting slack in access timings to improve performance, or implementing system-level RowHammer mitigations), we observe that designers today lack the necessary insight into commodity DRAM chips' reliability characteristics to implement these techniques in practice. In this work, we make a case for DRAM manufacturers to provide increased transparency into simple device characteristics (e.g., internal row address mapping, cell array organization) that a ect consumer-visible reliability. Doing so has negligible impact on manufacturers given that these characteristics can be reverse-engineered using known techniques; however, it has signi cant bene t for system designers, who can then make informed decisions to be er adapt commodity DRAM to meet modern systems' needs while preserving its cost advantages.To support our argument, we study four ways that system designers can adapt commodity DRAM chips to system-speci c design goals: (1) improving DRAM reliability; (2) reducing DRAM refresh overheads; (3) reducing DRAM access latency; and (4) defending against RowHammer a acks. We observe that adopting solutions for any of the four goals requires system designers to make assumptions about a DRAM chip's reliability characteristics. ese assumptions discourage system designers from using such solutions in practice due to the di culty of both making and relying upon the assumption.We identify DRAM standards as the root of the problem: current standards rigidly enforce a xed operating point with no speci cations for how a system designer might explore alternative operating points. To overcome this problem, we introduce a two-step approach that reevaluates DRAM standards with a focus on transparency of reliability characteristics so that system designers are encouraged to make the most of commodity DRAM technology for both current and future DRAM chips.

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Section: Information Flow During Testingmentioning

confidence: 99%

A Case for Transparent Reliability in DRAM Systems

Patel¹,

Shahroodi²,

Manglik³

et al. 2022

Preprint

View full text Add to dashboard Cite

show abstract

“…As process scaling continues, intermittent faults are of growing concern. Several field studies provide their characteristics [5], [7], [8], [30]: First, intermittent faults have been outgrowing other faults and will be the dominant challenge in memory reliability. Second, it is difficult to screen out all intermittent faults with testing.…”

Section: Dram Faults and Errorsmentioning

confidence: 99%

“…The importance of DRAM reliability is further growing as mission-critical systems (e.g., autonomous driving) require higher reliability and systems deploy more DRAM chips. Despite the demand, individual DRAM chips are becoming more vulnerable to faults and errors [5]- [8]. Process scaling has shrunk DRAM cells into nm-scale feature size and fF-scale cell capacitance.…”

Section: Introductionmentioning

confidence: 99%

On-Die Dynamic Remapping Cache: Strong and Independent Protection Against Intermittent Faults

Park

Kim

2022

IEEE Access

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As process scaling continues, DRAM is getting more vulnerable to errors. System companies and DRAM vendors have introduced ECC to protect DRAM against growing errors. ECC, however, should be combined with a repair mechanism to prevent non-transient faults from repeatedly producing errors and to prevent overlapping faults from accumulating into more severe errors. We propose a novel approach to repair memory and improve reliability with minimal overheads. On-die Dynamic Remapping Cache (DRC) minimizes the repair overheads by focusing on active faults. Most intermittent faults (e.g., Variable Retention Time) generate errors occasionally, and the number of active faults at any one time is significantly lower than the total. DRC tracks the activity and severity of faults at run-time and uses a small cache inside a DRAM to remap active faults. This efficiency enables aggressive remapping of bit faults, which eliminates fault accumulations and improves reliability. Our evaluation shows DRC can provide much stronger protection than the state-of-the-art protection schemes with no performance degradation and a negligible chip area overhead.

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“…We make three observations. First, HARP-U does not identify any bits at risk of indirect errors 11 because it bypasses the on-die ECC correction process that causes indirect errors. In contrast, HARP-A quickly identifies a subset of all bits at risk of indirect errors by predicting them from the identified direct errors.…”

mentioning

confidence: 99%

“…9 shows the worst-case (i.e., maximum) number of post-correction errors that can occur simultaneously within an ECC word after active profiling. 11 Except for a small number of direct and indirect errors that overlap. This number is the correction capability required from secondary ECC to safely perform reactive profiling.…”

mentioning

confidence: 99%

HARP: Practically and Effectively Identifying Uncorrectable Errors in Memory Chips That Use On-Die Error-Correcting Codes

Patel

Oliveira

Mutlu

2021

MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture

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Aggressive storage density scaling in modern main memories causes increasing error rates that are addressed using error-mitigation techniques. State-of-the-art techniques for addressing high error rates identify and repair bits that are at risk of error from within the memory controller. Unfortunately, modern main memory chips internally use on-die error correcting codes (on-die ECC) that obfuscate the memory controller's view of errors, complicating the process of identifying at-risk bits (i.e., error profiling).To understand the problems that on-die ECC causes for error profiling, we analytically study how on-die ECC changes the way that memory errors appear outside of the memory chip (e.g., to the memory controller). We show that on-die ECC introduces statistical dependence between errors in different bit positions, raising three key challenges for practical and effective error profiling: on-die ECC (1) exponentially increases the number of at-risk bits the profiler must identify; (2) makes individual at-risk bits more difficult to identify; and (3) interferes with commonly-used memory data patterns that are designed to make at-risk bits easier to identify.To address the three challenges, we introduce Hybrid Active-Reactive Profiling (HARP), a new error profiling algorithm that rapidly achieves full coverage of at-risk bits based on two key insights. First, errors that on-die ECC fails to correct have two sources:(1) direct errors from raw bit errors in the data portion of the ECC word and (2) indirect errors that on-die ECC introduces when facing uncorrectable errors. Second, the maximum number of indirect errors that can occur concurrently is limited to the correction capability of on-die ECC. HARP's key idea is to first identify all bits at risk of direct errors using existing profiling techniques with the help of small modifications to the on-die ECC mechanism. Then, a secondary ECC within the memory controller with correction capability equal to or greater than that of on-die ECC can safely identify bits at-risk of indirect errors, if and when they fail.We evaluate HARP in simulation relative to two state-of-the-art baseline error profiling algorithms. We show that HARP achieves full coverage of all at-risk bits faster (e.g., 99th-percentile coverage 20.6%/36.4%/52.9%/62.1% faster, on average, given 2/3/4/5 raw bit errors per ECC word) than the baseline algorithms, which sometimes fail to achieve full coverage. We perform a case study of how each

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Characterization of data retention faults in DRAM devices

Cited by 17 publications

References 16 publications

A Case for Transparent Reliability in DRAM Systems

A Case for Transparent Reliability in DRAM Systems

On-Die Dynamic Remapping Cache: Strong and Independent Protection Against Intermittent Faults

HARP: Practically and Effectively Identifying Uncorrectable Errors in Memory Chips That Use On-Die Error-Correcting Codes

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