Characterization of DAC Phase Offset in IEC 61850-9-2 Calibration Systems

Abstract

This paper presents an accurate and robust method to calculate the phase offset of a reference waveform, usually produced by a Digital-to-Analog Converter (DAC) in IEC Std 61850-9-2 calibration systems. The phase offset is defined with respect to the rising edge of a reference clock signal, locked to the Global Positioning System (GPS). The proposed method relies on the synchronous acquisition of the DAC output and the clock signal. In the complex plane, where the Discrete Fourier Transform (DFT) is defined, the acquired signals are processed in order to compensate the non-ideal sampling rate and windowing. The method performance as well as its dependence from noise and parameters, are thoroughly characterized by means of extensive numerical simulations. Two validation approaches, experimental and software-based, confirm the proposed method as a valuable and robust solution for calibration purposes.

Calibration of a Digital Current Transformer Measuring Bridge: Metrological Challenges and Uncertainty Contributions

“…The sampling rate is derived from the internal time base that is disciplined to the external time reference. In our setup, we are able to retrieve the coerced sampling rate on both boards and the discrepancy between nominal and actual sampling rate is equal to 0.3 ppb [18]. Therefore, it is reasonable to say that the sampling rate has a negligible effect on the amplitude, frequency and phase of the generated and re-acquired waveform.…”

“…In this context, it should be noticed that both DAC and ADC are typically equipped with two channels. One pair of channels (ai0 and ao1 in Figure 2) is dedicated to the test waveform generation and re-acquisition, whereas the other one (ai1 and ao0) is intended for self-calibration tasks, namely for the definition of the DAC phase offset [18], as further discussed in the following section; • A synchronization unit locked to the internal clock, and thus to the external time reference. The synchronization board is responsible for two main tasks: distributing the triggers for the other units within the calibrator, and providing the measuring bridge with a Pulse-Per-Second (PPS) signal that is aligned with the time-stamp of the SV data packets.…”

“…The time-series acquired at the two ADC input channels are processed via a DFTbased routine (further details in [18]) and the phase associated with the fundamental frequency is retrieved. In particular, channel ai1 is representative of the contribution of ADC only, whereas channel ai0 is representative of the entire measurement chain.…”

“…For this analysis, we considered a dataset of 100 independent acquisition with a sample length of 4 seconds. Moreover, we quantified the purity of the test waveform by means of a nonlinear fit against a single-tone sinusoidal model that produced a Goodness-of-Fit index not lower than 99.7% [18]. Based on these considerations, we quantified the DAQ contribution to the estimation of the current amplitude in terms of the noise variation range.…”

“…The recent EMPIR project FutureGrid II has been investigating the measurement needs and potential of SVs in modern electrical substations. In particular, dedicated calibration infrastructures for transmitting and receiving SVs have been developed and thoroughly characterized [17,18]. However, a rigorous and well-established procedure for the metrological characterization of NCITs is not yet available.…”