Characterization of an Oxidized Porous Silicon Layer by Complex Process Using RTO and the Fabrication of CPW-Type Stubs on an OPSL for RF Application

Park, Jeong-Yong; Lee, Jong‐Hyun

doi:10.4218/etrij.04.0103.0124

Cited by 3 publications

(4 citation statements)

References 8 publications

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“…4a). A small shift of the Raman-peak of bare porous silicon to lower wavenumbers compared to bulk-Si has also been observed in [9,10] and has been explained by stress of the PS-specimens caused by the anodization process. In the case of Ni-filled porous silicon the shift of the Raman-peak to lower wavenumbers is also caused by compressive stress due to the metal-filling of the pores.…”

Section: Resultsmentioning

confidence: 83%

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The interior interfaces of a semiconductor/metal nanocomposite and their influence on its physical properties

Granitzer

Rumpf

Poelt

et al. 2009

Phys. Status Solidi (c)

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A semiconductor/metal hybrid system with silicon as base material and embedded metal nanostructures is fabricated in two steps by anodizing the silicon substrate in an aqueous hydrofluoric acid solution and a subsequent electrodeposition process. The achieved self‐assembled nanoscopic hybrid system consists of a quasi‐regular 3‐dimensional arrangement of metal nanostructures embedded within the pores of the silicon matrix. The used metals are Ni, Co and their alloys, whereas mainly Ni is considered in the following. In such a hybrid system the interface between metal and silicon nanostructures is of interest in correlation with the properties of the material and can be influenced by different fabrication conditions. If the matrices are aged in ambient air before filling with a metal the inner surface of the porous silicon template offers a native SiOx layer due to the oxidation of the hydrogen terminated surface of the pore‐walls. Using as‐etched samples for deposition of the metal into the pores leads to the formation of a more complex interface during the cathodic deposition procedure which is observed by FTIR‐spectroscopy. Knowledge about the composition and the formation of the interior surface of the porous silicon matrix as well as the interface between semiconductor and metal is necessary on the one hand for interpretation of the gained experimental results and on the other hand to figure out possible applications of the fabricated hybrid system. (© 2009 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

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Section: Resultsmentioning

confidence: 83%

“…The obtained hysteresis loops do not show an asymmetry (Fig. 7) which means no exchange bias effect [10] is observed.…”

Section: Figure 5cmentioning

confidence: 79%

The interior interfaces of a semiconductor/metal nanocomposite and their influence on its physical properties

Granitzer

Rumpf

Poelt

et al. 2009

Phys. Status Solidi (c)

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“…4(b). Park and Lee (2004) reported that the band at 3500 cm −1 appears when porous silicon layers are partly oxidized and SiOH is formed on the surface. The results shown in Fig.…”

Section: Effect Of Additivesmentioning

confidence: 98%

Acceleration of groove formation in silicon using catalytic wire electrodes for development of a slicing technique

Salem

Lee

Ikeda

et al. 2010

Journal of Materials Processing Technology

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“…silicon wafer [10]- [13]. Probe beams were curled up as a result of surface tension and the difference in the thermal expansion coefficients between the thin films on the probe beams.…”

Section: Porous Silicon Micromachining Technologymentioning

confidence: 99%

Silicon Micro-probe Card Using Porous Silicon Micromachining Technology

Kim¹,

Yoon²,

Lee³

2005

ETRI J

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We present a new type of silicon micro-probe card using a three-dimensional probe beam of the cantilever type. It was fabricated using KOH and dry etching, a porous silicon micromachining technique, and an Au electroplating process. The cantilever-type probe beam had a thickness of 5 µm, a width of 50 µm, and a length of 800 µm. The probe beam for pad contact was formed by the thermal expansion coefficient difference between the films. The maximum height of the curled probe beam was 170 µm, and an annealing process was performed for 20 min at 500°C. The contact resistance of the newly fabricated probe card was less than 2 Ω, and its lifetime was more than 20,000 turns.

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Characterization of an Oxidized Porous Silicon Layer by Complex Process Using RTO and the Fabrication of CPW-Type Stubs on an OPSL for RF Application

Cited by 3 publications

References 8 publications

The interior interfaces of a semiconductor/metal nanocomposite and their influence on its physical properties

The interior interfaces of a semiconductor/metal nanocomposite and their influence on its physical properties

Acceleration of groove formation in silicon using catalytic wire electrodes for development of a slicing technique

Silicon Micro-probe Card Using Porous Silicon Micromachining Technology

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