Characterization of Alpha AXP performance using TP and SPEC workloads

Abstract

The characteristics of several commercial and technical workloads on the DEC 7000 AXP system are compared using built-in hardware monitors. The data analyzed include total instructions, cycles, multiple-issued instructions, stall components, cache misses, and instruction types. The data indicates that the two classes of Workloads have vastly different characteristics and impose different requirements on the system design.Compared to VAX, Alpha AXP takes advantage of lower cycles per instruction and cycle time to achieve a significant performance advantage. The cache and memory interconnect subsystems are expected to play a crucial role in the performance of future systems. A simple model for evaluating the effects of various design tradeoffs based on the data collected by using hardware monitors is proposed.

An analysis of database workload performance on simultaneous multithreaded processors

“…Overall, this data confirms the aggregate cache behavior of transaction processing workloads found by others; namely, that they suffer from higher miss rates than scientific codes (at least as exhibited by SPEC and SPLASH benchmarks), with instruction misses a particular problem [3,6,12,16]. For example, columns 2 and 3 of Table 3 show that on-chip caches are relatively ineffective both at current cache sizes (32KB) and at larger sizes (128KB) expected in next-generation processors.…”

“…Maynard, et al, [12] highlighted the large instruction footprints and high instruction cache miss rates of OLTP workloads. In another study, Cvetanovic and Bhandarkar [3] used performance counters on the DEC Alpha chip family (21064 and 21164) to identify the performance characteristics of a range of applications, including two commercial workloads.…”

“…Despite their increasing prominence, however, database management systems (DBMS) have been the subject of only limited architectural study [3,6,12,16,22]. Not surprisingly, these studies have shown that database systems can exhibit strikingly high cache miss rates.…”

Reducing coherence overhead and boosting performance of high-end SMP multiprocessors running a DSS workload

“…Other papers considered data base workloads and multiprocessor system configuration similar to ours [5,10,20,25,42,48]. However, their main focus deviates from ours.…”

“…From a multiprocessor design point of view, data base applications fall in the class of commercial workloads [20]. In the past, technical workloads were widely used to drive the design of current multiprocessor systems [35,10]. Different studies have shown that commercial workloads exhibit different behavior from technical ones, both in the general case [20] and in the OLTP system case [25].…”