Characterization of advanced gate stacks for Si CMOS by electron energy-loss spectroscopy in scanning transmission electron microscopy

Abstract

Novel metal oxide films and new metal gates are currently being developed for future generations of Si based field-effect transistors as the SiO 2 gate dielectric and polycrystalline Si gate electrode are reaching scaling limits. These new gate stacks are often comprised of subnanometer layers. Device properties are increasingly controlled by the complex structure and chemistry of interfaces between the layers. Electron energy loss spectroscopy (EELS) in scanning transmission electron microscopy (STEM) is capable of providing insights into interfacial chemistry and local atomic structure with a spatial resolution unmatched by any other technique. Using gate stacks with Hf-silicate dielectrics as examples, we demonstrate the capabilities of STEM/EELS for analyzing the interfacial chemistry of novel gate stacks. We show that a-priori unknown reaction layers of a few Å thickness can be detected and identified even in the presence of substantial interfacial roughness that may obscure such layers in a highresolution image. We discuss some experimental aspects of STEM/EELS chemical profiling applied to gate stacks and the factors affecting the interpretation. In particular, the effects of interfacial roughness, beam spreading, elemental analysis in a heavily scattering matrix, and the interpretation of the EELS core-loss fine-structures from ultrathin layers are discussed.

A new analytical method for characterising the bonding environment at rough interfaces in high-k gate stacks using electron energy loss spectroscopy

“…Equation (3) indicates that a plot of S(E) vs. (Lt-A o ) for a line spectrum image is also a straight line with gradient proportional to M(E) and intercept proportional to [I(E)-M(E)]. As indicated previously, sub-regions within the original spectrum image are used as individual data points for the S(E) vs. (Lt-A o ) plot provided the area A o can be estimated.…”

“…Figure 7(b) is a plot of the gradients of the least squares straight line fits to the experimental data at energy losses within the range of 95-200 eV. From equation (3), the gradient term is proportional to M(E) which in this particular case corresponds to the Si-L 2,3 edge from the poly-Si matrix phase. The standard error for the gradient term at each energy loss is also shown in figure 7(b) and has been multiplied by a factor of 10 for visual clarity.…”

“…Interface roughening can be caused by crystallisation, phase separation, interdiffusion, chemical reaction or may be due to a columnar grain structure. Electron energy loss spectroscopy (EELS) and energy dispersive X-ray (EDX) spectroscopy in a scanning transmission electron microscope (STEM) have been used previously to characterise the microstructure of high-k gate stacks, particularly at the interfaces [1][2][3][4][5][6][7]. For dielectrics involving Hf-Si-O with poly-Si gate electrodes, a silica (SiO 2 )-type layer has been observed at the dielectric/ gate electrode interface [1,3,5].…”

“…Electron energy loss spectroscopy (EELS) and energy dispersive X-ray (EDX) spectroscopy in a scanning transmission electron microscope (STEM) have been used previously to characterise the microstructure of high-k gate stacks, particularly at the interfaces [1][2][3][4][5][6][7]. For dielectrics involving Hf-Si-O with poly-Si gate electrodes, a silica (SiO 2 )-type layer has been observed at the dielectric/ gate electrode interface [1,3,5]. When a TiN metal gate is used in combination with HfO 2 or HfSiO, the interface between TiN and the subsequent polySi electrode showed a silicon oxynitride (SiO x N y ) interface layer [3,[6][7].…”

“…For dielectrics involving Hf-Si-O with poly-Si gate electrodes, a silica (SiO 2 )-type layer has been observed at the dielectric/ gate electrode interface [1,3,5]. When a TiN metal gate is used in combination with HfO 2 or HfSiO, the interface between TiN and the subsequent polySi electrode showed a silicon oxynitride (SiO x N y ) interface layer [3,[6][7]. However, a HfSiO dielectric with a TaN x gate showed only a SiO 2 interface layer [8].…”