Characterization of a low-power 6.4 Gbps DDR DIMM memory interface system

Power integrity of a 4.8Gbps-per-link low-swing single-ended-I/O server memory interface

“…The two PHYs were fabricated in 28nm CMOS and shown to perform well at 6.4Gb/s-per-link [1], a data rate that is well beyond what is currently expected of future DDR4 memory systems. Using high-speed single-ended signaling for high pin efficiency and aggregate interface bandwidth, good timing and voltage margins were also shown at 6.4Gb/s for a system with two dual-rank 16-device (16-D or single-row) DIMMs [2,3]. For the increased memory-system capacity required in the most demanding applications, higher-capacity, 36-memorydevice, dual-rank DIMMs were also fabricated but demonstrated at a lower data rate (4.8Gb/s) due to the added loss from extending the high-speed clock lines to drive a second row of MPHYs.…”