Characterization of 4.5 kV/2.4 kA press pack IGBT including comparison with IGCT

Alvarez, Rodrigo; Filsecker, Felipe; Buschendorf, Martin; Bernet, Steffen

doi:10.1109/ecce.2013.6646709

“…5.2, it is assumed in this paper that S cn is implemented by anti-parallel connection of two reverse-blocking IGCTs, such as those featured in [83]- [92]. Even though the IGCT is the preferred switch in applications with low switching frequencies, where the conduction power losses are dominant [84], [85], it is assumed to only be adopted for the high-efficiency links of the LMMC, due to its relatively high cost; the other switches are assumed to be of the IGBT type. Since terminal h is not used in the last network, switch S c(M−1) is not required.…”

Section: Discussionmentioning

confidence: 99%

Modelling, simulation, control, and enhanced topologies for the modular multilevel converter for high-voltage DC (HVDC) applications

Oliveira¹

2021

Preprint

1

0

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This thesis is focused on the modular multilevel converter (MMC) for High-Voltage DC (HVDC) systems. It is an attempt to address the issues associated with the modelling, simulation, control, efficiency, and fault-handling capability of the MMC. Thus, to address the modelling of the MMC, a new and more accurate steady-state harmonic model is proposed. The proposed harmonic model is capable of predicting the amplitude of the harmonic components of the MMC arm voltages, submodule capacitor voltages, and arm currents. Further, based on the proposed harmonic model, a capacitor sizing method is proposed to determine the capacitance of the submodule capacitor for a desired level of voltage variation, without a need for numerical algorithms or graphs used by the existing methods. In addition, the proposed capacitor sizing method can accurately determine the required capacitance even if circulating currents are injected to mitigate dc voltage fluctuations. The thesis also proposes a simple equivalent-circuit-based simulation model for MMC-based HVDC systems, which assumes ideal submodule switches to speed up the simulation, but is nonetheless capable of capturing the transients as well as harmonic components of the voltages and currents. Further, the thesis proposes a simple compensation strategy that calculates the magnitude of the second harmonic component of an arm voltage, and uses the calculated value as a feedforward signal to cancel the circulating current of the corresponding MMC leg. The proposed feedforward compensation strategy, if combined with a closed-loop circulating current suppression strategy, greatly mitigates the possibility of control saturation and, also, results in better damped closed-loop dynamics. Finally, the thesis proposes two new MMC topologies for enhanced efficiency and dc-side fault handling capability. In the first proposed topology, that is the lattice modular multilevel converter (LMMC), the entire MMC arm is modified to accommodate networks that allow shortcuts between the arm capacitors, thus, reducing conduction power losses of the converter. In the second topology proposed, however, only the submodule is modified. In the proposed submodule topology, referred to as lattice submodule (LSM), the conduction power losses are decreased, as it is the case for the LMMC, with the difference that the voltage stress in the switches are also reduced. Keywords: Control, lattice modular multilevel converter, lattice submodule, modelling, modular multilevel converter, simulation model.

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“…5.2, it is assumed in this paper that S cn is implemented by anti-parallel connection of two reverse-blocking IGCTs, such as those featured in [83]- [92]. Even though the IGCT is the preferred switch in applications with low switching frequencies, where the conduction power losses are dominant [84], [85], it is assumed to only be adopted for the high-efficiency links of the LMMC, due to its relatively high cost; the other switches are assumed to be of the IGBT type. Since terminal h is not used in the last network, switch S c(M−1) is not required.…”

Section: Discussionmentioning

confidence: 99%

Modelling, simulation, control, and enhanced topologies for the modular multilevel converter for high-voltage DC (HVDC) applications

Oliveira¹

2021

Preprint

0

View full text Add to dashboard Cite

This thesis is focused on the modular multilevel converter (MMC) for High-Voltage DC (HVDC) systems. It is an attempt to address the issues associated with the modelling, simulation, control, efficiency, and fault-handling capability of the MMC. Thus, to address the modelling of the MMC, a new and more accurate steady-state harmonic model is proposed. The proposed harmonic model is capable of predicting the amplitude of the harmonic components of the MMC arm voltages, submodule capacitor voltages, and arm currents. Further, based on the proposed harmonic model, a capacitor sizing method is proposed to determine the capacitance of the submodule capacitor for a desired level of voltage variation, without a need for numerical algorithms or graphs used by the existing methods. In addition, the proposed capacitor sizing method can accurately determine the required capacitance even if circulating currents are injected to mitigate dc voltage fluctuations. The thesis also proposes a simple equivalent-circuit-based simulation model for MMC-based HVDC systems, which assumes ideal submodule switches to speed up the simulation, but is nonetheless capable of capturing the transients as well as harmonic components of the voltages and currents. Further, the thesis proposes a simple compensation strategy that calculates the magnitude of the second harmonic component of an arm voltage, and uses the calculated value as a feedforward signal to cancel the circulating current of the corresponding MMC leg. The proposed feedforward compensation strategy, if combined with a closed-loop circulating current suppression strategy, greatly mitigates the possibility of control saturation and, also, results in better damped closed-loop dynamics. Finally, the thesis proposes two new MMC topologies for enhanced efficiency and dc-side fault handling capability. In the first proposed topology, that is the lattice modular multilevel converter (LMMC), the entire MMC arm is modified to accommodate networks that allow shortcuts between the arm capacitors, thus, reducing conduction power losses of the converter. In the second topology proposed, however, only the submodule is modified. In the proposed submodule topology, referred to as lattice submodule (LSM), the conduction power losses are decreased, as it is the case for the LMMC, with the difference that the voltage stress in the switches are also reduced. Keywords: Control, lattice modular multilevel converter, lattice submodule, modelling, modular multilevel converter, simulation model.

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“…The external clamping pressure should be determined by the total area of the chips, so as to ensure the electrical and mechanical properties of the Press-Pack IGBT device, reducing the thermal contact resistance and the electrical contact resistance between the components to a relatively low value. The stress should be around 12MPa [17] . The boundary conditions of the finite element simulation model are shown in Fig.…”

Section: Simulation Conditionsmentioning

confidence: 99%

Study of pressure balance for Press-Pack IGBTs and its influence on temperature distribution

Zhao

¹

,

Liang

²

,

Han

³

2018

Chin. J. Electr. Eng.

4

0

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Pressure balance is a key technology for Press-Pack IGBT packaging, and is studied in this paper with its influence on the temperature distribution discussed in further when the device is turned on. By establishing the physical model of the Press-Pack IGBT device in the finite element simulation software, the influence of the internal flatness condition on the pressure balance is analyzed, and the variation of the average pressure difference with the flatness in different parallel scale of the chips is obtained. The thermal contact resistance and the electrical contact resistance parameters, which are dependent on the pressure, are then imported to perform the multi-field coupling, further investigating the effect of different pressure distributions on temperature distribution. The junction-case thermal resistance of the device with different flatness is compared experimentally. The results have demonstrated the influence of the flatness on the thermal resistance of the Press-Pack IGBT device.

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Characterization of 4.5 kV/2.4 kA press pack IGBT including comparison with IGCT

Cited by 14 publications

References 14 publications

Modelling, simulation, control, and enhanced topologies for the modular multilevel converter for high-voltage DC (HVDC) applications

Modelling, simulation, control, and enhanced topologies for the modular multilevel converter for high-voltage DC (HVDC) applications

Modelling, simulation, control, and enhanced topologies for the modular multilevel converter for high-voltage DC (HVDC) applications

Study of pressure balance for Press-Pack IGBTs and its influence on temperature distribution

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