Characterization for Sub-5nm Technology Nodes of Junctionless Gate-All-Around Nanowire FETs

Direct current, analog/radio frequency device, and circuit applications of nanosheet (NS) field effect transistors were investigated. To enhance power performance, co-optimization geometry parameters like NS width (NSW) and NS thickness (NSH) are varied for high-performance and low-power applications. A rise of 1.47x in ION and a rise of 5.8x in IOFF is noticed with an increase in NSH due to enlarged effective width (Weff). In addition, a rise of 3.8x in ION and a fall of 76.4% in IOFF is noticed with higher NSW. Larger NSW ensures better transconductance, transconductance generation factor, cut-off frequency, gain-band width product, transconductance frequency product, and intrinsic delay. The optimized supply voltage for maximum voltage gain of common source amplifier and three stage ring oscillators (RO) with varied NSW was performed. The impact of number of stages (N) of three stage RO for better frequency of oscillations was studied for high-frequency circuit applications.

Section: Resultsmentioning

confidence: 99%

Common Source Amplifier and Ring Oscillator Circuit Performance Optimization Using Multi-Bridge Channel FETs

Sreenivasulu

Neelam

Vakkalakula

et al. 2023

“…24 As a result, for sub-5-nm nodes, the researchers came up with the solution of GAA FETs, in which the gate is present in all directions of the channel. 25,26 Nanosheet and Nanowire are renowned examples of GAA structures. As the gate surrounds the channel, the performance of the transistor increased substantially and made it possible to continue Moore's law further.…”

mentioning

confidence: 99%

Impact of Scaling on Nanosheet FET and CMOS Circuit Applications

Neelam

Sreenivasulu

Pothupogu

2023

The impact of scaling on the gate all around the nanosheet field effect transistor (NSFET) was studied in detail at sub-5-nm nodes for digital and analog/RF applications. When LG is scaled from 20 to 5 nm, ION is improved by 2.1×, IOFF increases by three orders of magnitude, SS increases by 27%, DIBL is increased by 4×, and a Vth roll off of 41 mV is noticed. Further, an enhancement of 3.65× was noticed in cut-off frequency (fT) with scaling of LG from 20 to 5 nm. The complimentary metal oxide semiconductor (CMOS) inverter and ring oscillator’s performance was studied in detail with LG scaling. With LG scaling from 20 to 5 nm, the inverter performance metrics like switching current is increased by 3.87×, propagation delay (τP), energy delay product and power delay product are reduced by 65%, 5.5× and 1.95×, respectively. Moreover, the ring oscillator offers superior performance with an oscillation frequency of 98.05 GHz when LG is scaled to 5nm, which is 157% more than fOSC at LG of 20 nm. Thus the analyses reveal the scaling capability of NSFET at both device and circuit levels for sub-5-nm nodes.

“…9 Further, the downscaling of transistors leads to many advantages like enhanced performance, low power consumption, increased functionality, and reduction in cost. Also, by reducing the dimensions of the MOSFET, it can be operated at lower supply voltages, 10,11 For lower technology nodes, the gate oxide thickness (t ox ) also needs to be scaled on par with the remaining dimensional parameters. In the year of 2003, the t ox reached around 1.2 nm for the 90 nm technology node.…”

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confidence: 99%

“…For sub-22nm technology nodes, FinFETs have proven to be capable of meeting the power and performance needs. However, for scaling of FinFETs for sub-5-nm nodes, thinner and taller fins are required to meet the performance criteria, 11,26 Maintaining such fins may lead to fabrication difficulties and hinders the performance of the device. At this juncture, the GAA FETs became the ultimate solution to continue the scaling of the transistor for sub-5-nm nodes.…”

mentioning

confidence: 99%

Spacer Engineering on Nanosheet FETs towards Device and Circuit Perspective

Kumari,

Sreenivasulu,

Ajayan

et al. 2023

For the first time, a nanosheet field effect transistor (NS FET) performance is demonstrated by incorporating various device engineering at both device and circuit levels. Various device topologies like lightly-doped drain/source, underlap, single and dual-k spacer are explored and the performance is compared with conventional NS FET. The NS FET with dual-k spacer is able to reduce the off current by 13.6× compared to the traditional NS FET. Further, the dual-k spacer offered good electrostatic performance and high switching ratio. Moreover, the analog/RF figures of merit are assessed for various device configurations. Though the dual-k spacer outperforms in terms of DC and analog metrics, the conventional NS FET can offer better RF metrics owing to the high current. Further, circuit level analysis is carried out using the Cadence tool for mixed circuit applications. The crucial circuits for IC design such as inverter, ring oscillator and common source (CS) amplifier are designed and evaluated the performance. The NS FET with dual-k spacer offers a gain of 1.815 for the CS amplifier and an oscillation frequency of 34.09 GHz for the 3-stage ring oscillator. The results will give insights into the performance of NS FET with various device architectures