ESSDERC 2007 - 37th European Solid State Device Research Conference 2007
DOI: 10.1109/essderc.2007.4430964
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Characterization and modeling of long term retention in SONOS non volatile memories

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Cited by 18 publications
(24 citation statements)
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“…Simple retention models identified electron tunneling through the tunnel oxide and thermal emission from the nitride as the two dominant charge loss processes in SONOS cells [4], [7]. However, the threshold voltage dynamics during retention could be affected also by the charge distribution at the beginning of the retention experiment [7], and by the spatial redistribution of the stored charge due to the transport in the nitride.…”
Section: Introductionmentioning
confidence: 98%
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“…Simple retention models identified electron tunneling through the tunnel oxide and thermal emission from the nitride as the two dominant charge loss processes in SONOS cells [4], [7]. However, the threshold voltage dynamics during retention could be affected also by the charge distribution at the beginning of the retention experiment [7], and by the spatial redistribution of the stored charge due to the transport in the nitride.…”
Section: Introductionmentioning
confidence: 98%
“…However, the threshold voltage dynamics during retention could be affected also by the charge distribution at the beginning of the retention experiment [7], and by the spatial redistribution of the stored charge due to the transport in the nitride. At this regard we note that, although the effective electron mobility in Si 3 N 4 reported by a few authors is low (∼0.1 cm 2 /(Vs) [8]), it is still large enough to induce significant changes on the charge spatial distribution even at low fields.…”
Section: Introductionmentioning
confidence: 99%
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“…Charge loss mechanisms of CT cells has been deeply investigated [13], identifying two main discharging paths: the first is related to thermal excitation of trapped carriers, the second one is due to direct tunneling through the thin tunnel oxide.…”
Section: Data Retentionmentioning
confidence: 99%
“…In this context, memories based on charge trapping layers, combined with high-k blocking oxides (as SANOS [1] and TANOS (TaN/Al2O3/SiN/SiO2/Si) [2] structures) are widely investigated for sub-32nm node generations. Several studies of TANOS-like structures have been presented, analyzing the retention mechanisms [3][4], proposing the optimization of the gate stack to improve the performances [5][6], or simulating the programming-erasingretention mechanisms [7]. Replacing SiO2 with a high-k material, as Al2O3, as top blocking layer of the conventional SONOS device increases the electric field across the tunnel oxide, while reducing the electric field across the blocking layer, during write and erase operations.…”
Section: Introductionmentioning
confidence: 99%