Characterization and mitigation of overlay error on silicon wafers with nonuniform stress

Brunner, Timothy A.; Menon, Vinayan C.; Wong, Cheuk Wun; Felix, Nelson; Pike, Michael; Gaidai, Oleg; Belyansky, M.; Vukkadala, Pradeep; Veeraraghavan, S.; Klein, S.; Hoo, C. H.; Sinha, Jaydeep K.

doi:10.1117/12.2045715

Cited by 14 publications

(12 citation statements)

References 2 publications

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“…During production, a processing tool that has a tendency to drift and cause process-induced overlay errors may be continuously monitored for excursion via shape measurements. Furthermore, it is envisioned that shape-based overlay predictions could be used in a feed-forward manner in order to allow for improved compensation of process-induced overlay errors during lithography exposure/scanning [8].…”

Section: Resultsmentioning

confidence: 99%

Monitoring process-induced overlay errors through high-resolution wafer geometry measurements

Turner

Vukkadala

Veeraraghavan

et al. 2014

Metrology, Inspection, and Process Control for Microlithography XXVIII

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Controlling overlay errors resulting from wafer processing, such as film deposition, is essential for meeting overlay budgets in future generations of devices. Out-of-plane distortions induced on the wafer due to processing are often monitored through high-resolution wafer geometry measurements. While such wafer geometry measurements provide information about the wafer distortion, mechanics models are required to connect such measurements to overlay errors, which result from in-plane distortions. The aim of this paper is to establish fundamental connections between the out-ofplane distortions that are characterized in wafer geometry measurements and the in-plane distortions on the wafer surface that lead to overlay errors. First, an analytical mechanics model is presented to provide insight into the connection between changes in wafer geometry and overlay. The analytical model demonstrates that the local slope of the change in wafer shape induced by the deposition of a residually stressed film is related to the induced overlay for simple geometries. Finite element modeling is then used to consider realistic wafer geometries and assess correlations between the local slope of the wafer shape change induced by the deposition of a stressed film and overlay. As established previously, overlay errors only result when the stresses in the film are non-uniform, thus the finite element study considers wafers with several different nonuniform residual stress distributions. Correlation between overlay and a metric based on a corrected wafer slope map is examined. The results of the modeling and simulations are discussed and compared to recently published experimental results.

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Section: Resultsmentioning

confidence: 99%

Monitoring process-induced overlay errors through high-resolution wafer geometry measurements

Turner

Vukkadala

Veeraraghavan

et al. 2014

Metrology, Inspection, and Process Control for Microlithography XXVIII

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“…This remarkable result is an indication of scanners inherent ability to control pattern placement. However, during the actual IC manufacture, the impact of overlay on EPE will be enhanced by a range of processrelated drivers 11,12 , and is expected to be larger than shown in figure 7. …”

Section: Statistics Of Triple-imaged Contact Pattern Critical Shape Ementioning

confidence: 95%

Lithographic imaging-driven pattern edge placement errors at 10nm node

et al. 2016

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Demand for ever increasing level of microelectronics integration continues unabated, driving the reduction of the integrated circuit critical dimensions, and escalating requirements for image overlay and pattern dimension control. The challenges to meet these demands are compounded by requirement that pattern edge placement errors be at single nanometer levels. Layout design together with the patterning tools performance play key roles in determining location of the pattern edges at different device layers. However, complexities of the layout design often lead to stringent tradeoffs for viable optical proximity correction and imaging strategy solutions. As a result, in addition to scanner overlay performance, pattern imaging plays a key role in the pattern edge placement. The imaging contributes to edge displacement by impacting the image dimensions and by shifting the images relative to their target locations. In this report we discuss various aspects of advanced image control at 10 nm integrated circuit design rules. We analyze the impact of pattern design and scanner performance on pattern edges. We present an example of complex, three step litho-etch patterning involving immersion scanners. We draw conclusion on edge placement control when complex images interact with wafer topography.

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“…Many factors can, through the complex wafer geometry changes (arising from deposition of films with nonuniform residual stress or bonding [16], in-plane stretching deformations induced by wafer chucking during lithography [17]), alter initially defined device patterns and their relative positions to alignment marks during wafer processing in-between exposure steps. In advanced silicon electronics manufacturing, high-resolution wafer geometry measurements combined with mechanics-based models are used as standard process control methods of predicting and correcting processing-induced overlay errors between lithography steps [18] to meet the ever-tightening error budgets. Unfortunately, implementation of such methods in practice is a complicated task and may not apply for less-mature Si photonics processing, thus semi-automatic (or even manual) alignment in less-modern DUV or electron beam lithography systems is generally used [15].…”

Section: Introductionmentioning

confidence: 99%

Comparison of processing-induced deformations of InP bonded to Si determined by e-beam metrology: Direct vs. adhesive bonding

Sakanas

Semenova

Ottaviano

et al. 2019

Microelectronic Engineering

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In this paper, we employ an electron beam writer as metrology tool to investigate distortion of an exposed pattern of alignment marks in heterogeneously bonded InP on silicon. After experimental study of three different bonding and processing configurations which represent typical on-chip photonic device fabrication conditions, the smallest degree of linearly-corrected distortion errors is obtained for the directly bonded wafer, with the alignment marks both formed and measured on the same InP layer side after bonding (equivalent to single-sided processing of the bonded layer). Under these conditions, multilayer exposure alignment accuracy is limited by the InP layer deformation after the initial pattern exposure mainly due to the mechanical wafer clamping in the e-beam cassette. Bonding-induced InP layer deformations dominate in cases of direct and BCB bonding when the alignment marks are formed on one InP wafer side, and measured after bonding and substrate removal from another (equivalent to double-sided processing of the bonded layer). The findings of this paper provide valuable insight into the origin of the multilayer exposure misalignment errors for the bonded III-V on Si wafers, and identify important measures that need to be taken to optimize the fabrication procedures for demonstration of efficient and high-performance on-chip photonic integrated devices.

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Characterization and mitigation of overlay error on silicon wafers with nonuniform stress

Cited by 14 publications

References 2 publications

Monitoring process-induced overlay errors through high-resolution wafer geometry measurements

Monitoring process-induced overlay errors through high-resolution wafer geometry measurements

Lithographic imaging-driven pattern edge placement errors at 10nm node

Comparison of processing-induced deformations of InP bonded to Si determined by e-beam metrology: Direct vs. adhesive bonding

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