Characterization and integration of new porous low-k dielectric (k&lt;2.3) for 65 nm technology and beyond

Choi, Kwang Hyun; Cho, Ihl Hyun; Park, Sang Jong; Lim, Ji-Young; Jung, Oh Jin; Park, Jong Hyuk; Min, Byung Seung; Hwang, Sung Bo; Ko, Min Jin; Lee, Jeong Gun

doi:10.1016/j.tsf.2006.10.096

Cited by 6 publications

(5 citation statements)

References 10 publications

(7 reference statements)

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“…In this experiment, 100 nm PECVD TEOS films, CMP, ash, and etch, 1 level metallization integration by the single damascene method was performed to deposit electrolessplated Ni-B films on the 100 nm Cu films [24]. Where the electroless-plated Ni-B films were deposited at the bath temperature of 70 °C using a Ni plating solution bath (pH = 5.6) including dimethylamine borane (DMAB).…”

Section: Ni-b Films Deposition On Single Cu Damascenementioning

confidence: 99%

In-situ temperature-dependent sheet resistance study of Cu films in oxygen ambient for heterogeneous integrations

Chavan,

Kim,

Choi

et al. 2024

Nanotechnology

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Controlling and preventing Cu oxidation is crucial for improving the performance and reliability of Cu-Cu bonding. Ni-B films were selectively deposited on Cu films to block the Cu oxidation. The resistivity changes of the Cu films in N2 and O2 ambient were measured by using a four-point probe in the in-situ temperature-dependent resistance measurements at the temperature from room temperature to 400°C. The resistivity changes of the 100nm-thick Cu films without Ni-B increased rapidly at a higher temperature (284°C) in the O2 ambiance. The change of resistivity-increase of 100nm-thick Cu with ~50 nm-thick Ni-B (top) film was lower than the Cu films without Ni-B films due to the blocking diffusion of O2 atoms by the Ni-B films. The resistivity-change and oxidation barrier properties were studied using SEM, FIB, TEM, EDX, and SIMS tools. The proposed article will be helpful for the upcoming advancement in Cu-Cu bonding using selected-area deposition.

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Section: Ni-b Films Deposition On Single Cu Damascenementioning

confidence: 99%

In-situ temperature-dependent sheet resistance study of Cu films in oxygen ambient for heterogeneous integrations

Chavan,

Kim,

Choi

et al. 2024

Nanotechnology

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“…In a previous study we found that silicate (SiO x ) is a good protective capping layer material for low-k PMSSQ dielectric layer and, furthermore, its adhesion to the low-k dielectric layer can be improved signicantly aer a carbon dioxide (CO 2 ) plasma treatment of the dielectric layer surface. 18 Taking this fact into account, a 80 nm thick SiO x capping layer was deposited on the top of the CO 2 plasma treated low-k dielectric layers by thermal deposition of tetraethoxysilane (TEOS) and put under subsequent curing at 400 C for 2 h in nitrogen atmosphere (S2 in Scheme 1). To realize damascene low-k lm stack, a multilayer stack structure, Si/SiC (30 nm thick)/low-k lm (200 nm)/SiO x (80 nm)/tantalum (Ta, 5 nm)/tantalum nitride (TaN, 30 nm)/Cu seed (100 nm)/Cu (500 nm) was introduced.…”

Section: Experimental Partmentioning

confidence: 99%

Structural reliability evaluation of low-k nanoporous dielectric interlayers integrated into microelectronic devices

et al. 2015

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“…Due to the high resistance resulting from the fluorine reactivity with metal lines such as Al or Cu, organosilicate glass (OSG) with good resistance to oxidation has been developed as below 90 nm technology node devices with low dielectric constant below 2.9. [13][14][15][16] Evaluation of the barriers in Cu interconnections has involved a metal-oxide-semiconductor * Author to whom correspondence should be addressed.…”

Section: Introductionmentioning

confidence: 99%

Effect of Ashing Conditions and Optimization of Nano Process Integration in Copper/Porous Low-k Nano-Interconnects

Pyo

Kim²

2012

j nanosci nanotechnol

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We report the optimization of ashing conditions and the process integration of a chemical vapor deposition (CVD) ultra low-k (k = 2.2) organosilicate (OSG) dielectric in a top hard mask damascene structure. The N2/H2 ash showed the lowest resistance-capacitance (RC) product and a dual top hard mask approach for dual damascene processing was built, using 200 nm SiC/50 nm SiO2 as the hard mask. This CVD low-k material had no low-k voiding, unlike other spin-on dielectric (SOD) low-k materials. The presence of the densified layer around the trench during the ashing process could improve the precursor penetration during the CVD barrier metal deposition process.

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Characterization and integration of new porous low-k dielectric (k<2.3) for 65 nm technology and beyond

Cited by 6 publications

References 10 publications

In-situ temperature-dependent sheet resistance study of Cu films in oxygen ambient for heterogeneous integrations

In-situ temperature-dependent sheet resistance study of Cu films in oxygen ambient for heterogeneous integrations

Structural reliability evaluation of low-k nanoporous dielectric interlayers integrated into microelectronic devices

Effect of Ashing Conditions and Optimization of Nano Process Integration in Copper/Porous Low-k Nano-Interconnects

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