“…The calibrated silicon (Si) nanosheet device is with the gate length of 12 nm, the nanosheet thickness of 5 nm, the nanosheet width of 25 nm, the effective oxide thickness of 0.66 nm, the spacing between the channels of 10 nm, and both S and D extensions of 5 nm. The workfunction of titanium nitride (TiN), the interface trap density and the lattice temperature are tuned [ 26 ] to align the measurement. Fig.…”
Section: Methodsmentioning
confidence: 99%
“…Figure 2 d, e shows cross sections of the 3D structure along different directions. In order to reduce the source/drain (S/D) resistance, the metal sidewall [ 26 ] is employed to increase I on , as shown in Fig. 2 e. The inter layer dielectric (ILD) is SiO 2 and the metal gate is TiN in Fig.…”
In this paper, we computationally study electrical characteristics for gate-all-around fin field effect transistors (GAA FinFETs) and negative capacitance GAA FinFETs (NC-GAA FinFETs) for sub-3-nm technological nodes. For the devices with the fin height of 55 nm, the on-state current increases (about 33% improvement) and the off-state current decreases (about 73% suppression) due to the NC effect. NC-GAA FinFETs have larger standard deviation of threshold voltage induced by the workfunction fluctuation (WKF) for both N-/P-type devices than those of GAA FinFETs. It is attributed to the variation of polarization in the different position of the ferroelectric layer. Notably, the inverter of NC-GAA FinFETs has larger noise margin and shorter delay time, compared with the inverter of GAA FinFETs; however, the characteristics of inverter of NC-GAA FinFETs suffer larger variability induced by the WKF.
“…The calibrated silicon (Si) nanosheet device is with the gate length of 12 nm, the nanosheet thickness of 5 nm, the nanosheet width of 25 nm, the effective oxide thickness of 0.66 nm, the spacing between the channels of 10 nm, and both S and D extensions of 5 nm. The workfunction of titanium nitride (TiN), the interface trap density and the lattice temperature are tuned [ 26 ] to align the measurement. Fig.…”
Section: Methodsmentioning
confidence: 99%
“…Figure 2 d, e shows cross sections of the 3D structure along different directions. In order to reduce the source/drain (S/D) resistance, the metal sidewall [ 26 ] is employed to increase I on , as shown in Fig. 2 e. The inter layer dielectric (ILD) is SiO 2 and the metal gate is TiN in Fig.…”
In this paper, we computationally study electrical characteristics for gate-all-around fin field effect transistors (GAA FinFETs) and negative capacitance GAA FinFETs (NC-GAA FinFETs) for sub-3-nm technological nodes. For the devices with the fin height of 55 nm, the on-state current increases (about 33% improvement) and the off-state current decreases (about 73% suppression) due to the NC effect. NC-GAA FinFETs have larger standard deviation of threshold voltage induced by the workfunction fluctuation (WKF) for both N-/P-type devices than those of GAA FinFETs. It is attributed to the variation of polarization in the different position of the ferroelectric layer. Notably, the inverter of NC-GAA FinFETs has larger noise margin and shorter delay time, compared with the inverter of GAA FinFETs; however, the characteristics of inverter of NC-GAA FinFETs suffer larger variability induced by the WKF.
“…Although some literatures shows studies on NS-FET, [10][11][12] the qualitative analysis of geometry variation of NS W and NS H towards analog and mixed-mode circuit performance still need relavent discussion. Moreover, the dependency of NS W and NS H on DC, analog and RF metrics is also performed.…”
Direct current, analog/radio frequency device, and circuit applications of nanosheet (NS) field effect transistors were investigated. To enhance power performance, co-optimization geometry parameters like NS width (NSW) and NS thickness (NSH) are varied for high-performance and low-power applications. A rise of 1.47x in ION and a rise of 5.8x in IOFF is noticed with an increase in NSH due to enlarged effective width (Weff). In addition, a rise of 3.8x in ION and a fall of 76.4% in IOFF is noticed with higher NSW. Larger NSW ensures better transconductance, transconductance generation factor, cut-off frequency, gain-band width product, transconductance frequency product, and intrinsic delay. The optimized supply voltage for maximum voltage gain of common source amplifier and three stage ring oscillators (RO) with varied NSW was performed. The impact of number of stages (N) of three stage RO for better frequency of oscillations was studied for high-frequency circuit applications.
“…These trends follow up the path towards the law stated by Moore. 1,2 According to Moore's law, the number of transistors on a chip has to be twice for every one and a half year. 3 Abiding by this law miniaturization of the transistor can be done, providing enhanced performance, high throughput, reduced energy consumption, and remarkable speed.…”
Moore's law states that the technical innovations are being absorbed already. The device's controllability has dramatically improved since moving from a straightforward metal oxide semiconductor field effect transistor (FET) constructed with a single control gate to one with many control gates. Here, the device-level simulation of vertically stacked GAA nanosheet FET is performed, for which the various geometrical variations are calibrated to examine the impact of these geometrical variations on the device's performance. The most prominent parameters like ION, IOFF, SS, DIBL, switching ratio, and threshold voltage values are analyzed. For the device to be considered to have better performance ION should be maximum, IOFF should be minimum. Hence, to obtain this, the thickness of the nanosheet is varied on the scale of 5 to 9 nm, and the width is varied from 10 to 50 nm. The device simulation and analysis are performed using the Visual TCAD - 3D Cogenda tool.
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