Chaotic Ring Oscillator Based True Random Number Generator Implementations in FPGA

Zacharias, Ajish; Gisha, C G; Jose, Babita R.

doi:10.1109/vdat50263.2020.9190505

Cited by 6 publications

(1 citation statement)

References 16 publications

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“…On the other hand, programmable hardware and programmable System on Chip are gaining large adoption rate, also in a security-critical application, where high-quality random number generation is mandatory. Digital TRNGs can be implemented using logic gates only, exploiting digital sources of randomness, such as supply voltage noise [10,11] metastability [12][13][14] and jitter [15][16][17]: the area footprint, in this case, is dramatically reduced by the absence of analogue circuitry and the consequent possibility of mapping all the design in digital standard-cell.…”

Section: Introduction: Random Number Generation For Securitymentioning

confidence: 99%

True Random Number Generator Based on Fibonacci-Galois Ring Oscillators for FPGA

et al. 2021

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Random numbers are widely employed in cryptography and security applications. If the generation process is weak, the whole chain of security can be compromised: these weaknesses could be exploited by an attacker to retrieve the information, breaking even the most robust implementation of a cipher. Due to their intrinsic close relationship with analogue parameters of the circuit, True Random Number Generators are usually tailored on specific silicon technology and are not easily scalable on programmable hardware, without affecting their entropy. On the other hand, programmable hardware and programmable System on Chip are gaining large adoption rate, also in security critical application, where high quality random number generation is mandatory. The work presented herein describes the design and the validation of a digital True Random Number Generator for cryptographically secure applications on Field Programmable Gate Array. After a preliminary study of literature and standards specifying requirements for random number generation, the design flow is illustrated, from specifications definition to the synthesis phase. Several solutions have been studied to assess their performances on a Field Programmable Gate Array device, with the aim to select the highest performance architecture. The proposed designs have been tested and validated, employing official test suites released by NIST standardization body, assessing the independence from the place and route and the randomness degree of the generated output. An architecture derived from the Fibonacci-Galois Ring Oscillator has been selected and synthesized on Intel Stratix IV, supporting throughput up to 400 Mbps. The achieved entropy in the best configuration is greater than 0.995.

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