ChangeSUB: A power efficient multiple network-on-chip architecture

Baharloo, Mohammad; Aligholipour, Rashid; Abdollahi, Meisam; Khonsari, Ahmad

doi:10.1016/j.compeleceng.2020.106578

Cited by 24 publications

(11 citation statements)

References 9 publications

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“…PT = Pd + Ps + Psc On the other hand, the comparison between the static and dynamic power estimation for the two technology shown in figures 2 and 3 clearly proves that the use of new technology implies static energy becomes more important. M. Baharloo et al [24] also represents the static power of the total NoC power in different CMOS technology nodes. The static power has risen from 42% to 64% following a technology update from 45nm down to 22nm.…”

Section: Energy Consumptionmentioning

confidence: 99%

“…Called the minimum performance penalty, this schema shows a decrease in terms of performance penalties and increasing static energy, this approach has been tested using PARSEC benchmarks. In addition, discover that the network architecture has an impact on the performance of the system M. Baharloo et al [24] used a multi network on chip instead of NoC, which has improved performance especially on power consumption.…”

Section: Energy Consumptionmentioning

confidence: 99%

“…Bouhadiba et al [26] proposed a study on energy consumption at TLM level based on a real FPGA system, designed with Xilinx EDK. Studies such as M.Baharloo et al [24] propose models to make the estimation power of systems on chip, the first in an RTL level with a NOC (R. Garibotti et al 2015) network and the second with a bus network at TLM level L. Caiet al [27]. The results show the accuracy of the two models and the good results in terms of energy in high levels of abstraction.…”

Section: Energy Consumptionmentioning

confidence: 99%

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A Review of the Different Levels of Abstraction for Systems-on-Chip (SoC)

et al. 2021

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Simulating systems on a chip (SoC) even before starting its productivity makes it possible to validate the correct functioning of the systems, also avoiding the manufacture of defective chips. However, low-level design and system complexity makes verification and simulation more complicated and time consuming. The classification of the different levels of abstraction from lowest to highest generally depends on the estimation accuracy of the system performance and the speed of simulation. The RTL (Register Transfer Level) abstraction level allows efficient description at gate level with good precision. Therefore, RTL program are slowly simulated. Simulation speed usually depends on the size of the platform used, which is not the case for transaction level modeling (TLM) to achieve simulation speed based on the exchange of transactions between system modules. This work aims to give a detailed description of the different levels of abstraction with the main advantages, and disadvantages on the performances estimation side such as, energy consumption, precision, and speed. Furthermore, an overview of the most adequate memory architectures and interconnection networks, to aim the most suitable virtual platforms of simulation for SoC.

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Section: Energy Consumptionmentioning

confidence: 99%

Section: Energy Consumptionmentioning

confidence: 99%

Section: Energy Consumptionmentioning

confidence: 99%

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A Review of the Different Levels of Abstraction for Systems-on-Chip (SoC)

et al. 2021

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“…By 1990s, System-on-Chip has been proposed where many modules such as microprocessor, custom IP and analog incorporated in a sole chip. As SoC complication raises, it is hard to sum up the system's functionality with fully deterministic operations [1].…”

Section: Introductionmentioning

confidence: 99%

“…In the multiple NoC utilize the few active small subnets to handle the traffic. In this proposed architecture can changed the microarchitecture routers to the implemented of non-zero subnets.The packet average latency or the performance time of various standards comparing to the traditional multi network on chip is decreases the structure by the 4.5%, and 10.5% singly, while the acquired area overhead is simply about 1.9% [1]. Figure 1.…”

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confidence: 97%

Low power network on chip architectures: A survey

Naqvi

2020

Comput. Sci. Inf. Technol.

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Mostly communication now days is done through SoC (system on chip) models so, NoC (network on chip) architecture is most appropriate solution for better performance. However, one of major flaws in this architecture is power consumption. To gain high performance through this type of architecture it is necessary to confirm power consumption while designing this. Use of power should be diminished in every region of network chip architecture. Lasting power consumption can be lessened by reaching alterations in network routers and other devices used to form that network. This research mainly focusses on state-of-the-art methods for designing NoC architecture and techniques to reduce power consumption in those architectures like, network architecture, network links between nodes, network design, and routers.

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RRW: A Reliable Ring Waveguide-Based Optical Router for Photonic Network-on-Chips

Fadhel

Huang

2021

Communications in Computer and Information Science

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ChangeSUB: A power efficient multiple network-on-chip architecture

Cited by 24 publications

References 9 publications

A Review of the Different Levels of Abstraction for Systems-on-Chip (SoC)

A Review of the Different Levels of Abstraction for Systems-on-Chip (SoC)

Low power network on chip architectures: A survey

RRW: A Reliable Ring Waveguide-Based Optical Router for Photonic Network-on-Chips

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