Challenges with Respect to High-k/Metal Gate Stack Etching and Cleaning

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Lanthanum oxide (La x O y ) and magnesium oxide (Mg x O y ) high-k cap-dielectrics have been used to modulate the effective work function for high-k/metal gate CMOS devices. The use of DIW during wet processing leads to unacceptable material loss due to the high solubility of materials. In this work, new rinsing procedures with pH-controlled and solvent-based solutions were evaluated in order to avoid material loss. It is validated that both pH-controlled (> pH 10) and solvent-based solutions achieve less than 1 Å of La 2 O 3 loss and solvent-based solutions can well be used on MgO 2 , providing less than 1 Å loss. Furthermore, no adverse affects, such as an increase in particle or surface roughness, were observed by applying the new rinsing procedures.

Section: Introductionmentioning

confidence: 99%

New Wet Process Strategies for Reduced La₂O₃ and MgO₂ High-k Cap-dielectric Loss

Wada¹,

Vos²,

Claes³

et al. 2009

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“…Typical wet etch chemistries for Hf-based materials are diluted hydrofluoric acid (HF)-based solutions, where hydrochloric acid (HCl) is added to improve the selectivity towards SiO 2 . In contrast, La 2 O 3 is soluble in HCl, but forms insoluble LaF 3 in HF solutions and as such forms particles [3]. Clearly the removal of La 2 O 3 /HfO 2 stacks is challenged by this apparent chemistry incompatibility.…”

Section: Introductionmentioning

confidence: 99%

Interplay between Dry Etch and Wet Clean in Patterning La₂O₃/HfO₂ Containing High-k/metal Gate Stacks

Vos¹,

Hellin

Vrancken³

et al. 2009

A dry-wet patterning process for La 2 O 3 /HfO 2 -containing high-κ/ metal gate stacks was successfully developed. The process meets the stringent requirements of complete removal of the high-κ layers and metal-containing sidewall residues without inducing silicon recess or undercut. The interaction between the dry etch and wet clean steps was studied. Use of a BCl 3 -based plasma process facilitated the cleaning process as it damages and modifies the high-κ layers in the active area. When the dry etch process ends with a BCl 3 step, La-containing residues were formed inhomogeneously over the wafer within the time scale of hours. These residues could no longer be removed with a wet clean, but were not observed when the dry etch and wet clean processes were integrated. This demonstrates that an integrated etch-clean process enlarges the process window.

“…It is well known that rare-earth oxides show strong tolerance to RIE (reactive ion etching) because of their low volatility characteristic and the development of wet-cleaning technology is thus appropriate for its removal processing. It has already been pointed out that the rare-earth-oxides are fluorinated by aqueous HF treatment [3]. These rare-earth-fluorides, such as LaF 3 , are insoluble in water and often remain on processed wafer surfaces as residue.…”

Section: Introductionmentioning

confidence: 99%

Structural Changes of La₂O₃-doped Hf-based High-k Dielectrics during Aqueous HF Treatment

Sugita¹,

Hayashi²,

Aoyama³

et al. 2009

The wet removal of La 2 O 3 -doped Hf-based dielectrics is examined for future high-k metal-insulator-semiconductor field-effecttransistor (MIS-FET) processing. XPS observations reveal that aqueous HF treatment removes Hf and Si components from La 2 O 3 -doped HfSiON, and LaF x residue remains on the processed wafer surface. It is shown that the sequential treatment of strong acid and HF is effective to reduce unfavorable LaF x adhesion. It is pointed out that HF-treatment fluorinates La in HfO 2 film with no-filmdissolution and reactive-ion-etching (RIE) must be selected to remove La 2 O 3 -doped HfO 2 film. To clarify the effect of removal processing on actual MIS-FET structures, SEM and high resolution STEM observations are carried out. The observations suggest that both the side etching of HfSiON dielectrics during HF-treatment and the substrate recess during HfO 2 film removal with RIE are serious issues for the manufacturing of La 2 O 3 -doped high-k MISFETs.