2022
DOI: 10.1002/adma.202109796
|View full text |Cite
|
Sign up to set email alerts
|

Challenges of Wafer‐Scale Integration of 2D Semiconductors for High‐Performance Transistor Circuits

Abstract: Large‐area 2D‐material‐based devices may find applications as sensor or photonics devices or can be incorporated in the back end of line (BEOL) to provide additional functionality. The introduction of highly scaled 2D‐based circuits for high‐performance logic applications in production is projected to be implemented after the Si‐sheet‐based CFET devices. Here, a view on the requirements needed for full wafer integration of aggressively scaled 2D‐based logic circuits, the status of developments, and the definit… Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2
1
1

Citation Types

0
19
0

Year Published

2022
2022
2024
2024

Publication Types

Select...
9

Relationship

0
9

Authors

Journals

citations
Cited by 40 publications
(22 citation statements)
references
References 44 publications
(79 reference statements)
0
19
0
Order By: Relevance
“…[ 66 ] However, their wafer‐scale synthesis is still in the early stages of development, and their production processes are not yet as mature or cost‐effective as those for metal oxides. [ 67 ] As research and development efforts continue and more efficient synthesis methods are developed, the cost‐effectiveness and scalability of wafer‐scale production for these 2D materials are expected to improve.…”
Section: Future Outlookmentioning
confidence: 99%
“…[ 66 ] However, their wafer‐scale synthesis is still in the early stages of development, and their production processes are not yet as mature or cost‐effective as those for metal oxides. [ 67 ] As research and development efforts continue and more efficient synthesis methods are developed, the cost‐effectiveness and scalability of wafer‐scale production for these 2D materials are expected to improve.…”
Section: Future Outlookmentioning
confidence: 99%
“…Incorporating a back-gate on a wafer-scale makes it difficult (or impossible) to control the electrostatics of each transistor’s gate independently. Therefore, for CMOS integration, once again, BEOL compatible solutions are being investigated [ 132 , 133 , 134 , 135 , 136 , 137 ]. However, BEOL integration comes with its own problems, as discussed in the chemiresistive section, in that the thermal budget is significantly reduced, the insulators are of lower quality, and mass production is very challenging.…”
Section: Semiconductor-based Gas Sensor Typesmentioning
confidence: 99%
“…20,21 With the recent advances in the synthetic growth of 2D semiconductors and gradual improvements in their quality, [22][23][24] the 2D semiconductor/ dielectric interface has become a dominant factor in limiting the device performance. 25,26 Hence, it is imperative to understand the 2D semiconductor/dielectric interface for further improvements in the performance and reliability of 2D material-based devices.…”
Section: Introductionmentioning
confidence: 99%