Challenges in worldwide IP reuse

Abstract

Advances in IC process technology have enabled the design of complex systems on a single chip. System-on-chip developers need to be able to mix and match pre-designed, best-in-class functional blocks from many providers if they are to meet design deadlines with limited design engineering resources. Consequently, there is a rising interest in the creation, distribution, and design application of reusable, interoperable blocks of intellectual property, referred to as "IP" or "virtual components." This panel will explore the opportunities and challenges for design innovation offered by a worldwide, open reuse mechanism for virtual components.The session will begin with an embedded tutorial case study on the VSIA (Virtual Socket Interface Alliance) approach to design reuse. Then IP providers and users will discuss the technical and business challenges in establishing a mechanism for reuse of virtual components. The panelists will also discuss the issues in integrating virtual components from multiple providers into system-onchip designs. Doug Fairbairn, Cadence Design Systems Larry Cooke, Toshiba America Electronic ComponentsThe VSI Alliance was formed to help drive a common vision for the use of complex cores in the electronics industry and break down the technical barriers to the mix and match of 1P in system-on-chip design, including new concepts such as "virtual components" and the "virtual socket interface." This tutorial will describe the background of the VSI Alliance, including the industry forces which brought it into existence. We will present the first results of the Alliance, including the VSI Architectural Document and Roadmap and how these can be applied to system-on-chip design. We will also provide a brief review and description of potential impact of the Alliance's work in progress in areas such as IP protection, mixed-signal design, manufacturing test, system-level design, implementationlverification, and on-chip bus standards. Steve Schulz, Texas InstrumentsAfter evaluation, virtual components will be designed into the system-chips of the future using new methodologies. This presentation will cover how virtual components are captured, starting from an English requirements definition through the conversion to netlists, including hardwarelsoftware, board, ASIC, and FPGA technologies. It will also describe how virtual components are captured when netlists are converted to real physical instantiations. There will be descriptions of the documentation, formats, and design interfaces required to facilitate "plug-and-play" productivity gains, as well as realistic views of required application support for various types of virtual components, Takahide Inoue, SonyProbably the most profitable and often-used virtual components in system houses are standard formats such as NTSC, Ethernet, and PCI bus. The emerging System-on-Chip (SoC) integration capabilities require system industries and semiconductor manufacturers to develop strong technical and business collaborations, since now more than ever, SoCs must be d...

Behavioral IP specification and integration framework for high-level design reuse

“…Because of the growing complexity of SoC designs [2], design reuse methodologies are known as the better way to bridge the gap between performance and time-to-market [15,13] with nowadays methodologies and tools. For IP integrators, the challenges consist in understanding all the specifications of existing blocks responding to his needs, and in testing and interface development [9,10]. Unfortunately, IP reuse lacks design methodologies and tools facing these problems.…”