Challenges for patterning process models applied to large scale

Abstract

Full-chip patterning simulation has been utilized in semiconductor manufacturing for more than ten years, and has been a key enabler for multiple technology generations, from 130 nm to the emerging 14 nm node. This span has featured two wavelength changes, a progression of optical NA increases (and a subsequent decrease), and a variety of patterning processes and chemistries. Full-chip patterning simulations utilize quasirigorous optical models and semiempirical resist and etch process models. There has been steady improvement in the predictive power and computational efficiency of the patterning models used in full chip simulation tools, and this paper will review this progress as well as the factors that ultimately limit the predictive capability of such models. In addition, this paper will outline the new process simulation challenges that are emerging as the industry approaches sub-0.25 k1 patterning. These challenges lie principally in improving accuracy and predictive capability, including 3D effects, for an expanding set of processes and failure modes, while maintaining or improving full chip data preparation cycle times.

Intensity Difference Map (IDM) Accuracy Analysis for OPC Efficiency Verification and Further Enhancement

“…(2). Notice that, for realistic industrial cases, a generalized formulation of CTR model is exploited, wherein, Gaussian kernel is included in wafer image computation [24], [25], [26]. For advanced technology nodes, more complicated resist models, such as, Variable Threshold Resist (VTR) might be required [27].…”

14-nm photomask simulation sensitivity

“…For imaging mask transparent spaces to print photoresist holes with positive-tone systems on wafer, OMOG was demonstrated in many cases to deliver improved process window over attPSM at 45 to 28-nm technologies. For imaging mask absorbing lines to print wafer spaces with negative-tone develop, attPSM has an advantage in some cases 8 . Since the attPSM is approximately 40% thicker than OMOG, this will increase the contribution from mask 3D EMF effects, and will drive further adoption of 3DEMF mask full-chip computational models.…”

Optical proximity correction: A cross road of data flows

“…Figure 1 illustrates this by showing the different "models" that are involved in the iterative generation of an OPCed mask, given a certain target design. In each iteration, the expected wafer pattern is calculated for the assumed mask as follows: 3,4) (1) The optical image intensity is calculated in one or more planes inside the resist. If the mask is assumed to be "perfect", this step only requires an optical model.…”