Challenges and Progress in Germanium-on-Insulator Materials and Device Development towards ULSI Integration

Augendre, E.; Sanchez, L.; Benaissa, L.; Signamarcheix, T.; Hartmann, Jean‐Michel; Royer, C. Le; Vinet, M.; Daele, W. Van Den; Damlencourt, Jean‐François; Romanjek, K.; Pouydebasque, A.; Batude, P.; Tabone, C.; Mazen, F.; Tauzin, A.; Blanc, Nicolas; Pellat, M.; Dechamp, J.; Zussy, M.; Scheiblin, P.; Jaud, Marie-Anne; Drazek, Charlotte; Maurois, C; Piccin, M.; Abbadie, A.; Lallement, F.; Daval, N.; Guiot, Eric; Rigny, Arnaud; Ghyselen, B.; Bourdelle, K.K.; Boulanger, F.; Cristoloveanu, S.; Billon, T.; Faynot, O.; Deguet, C.; Clavelier, L.

doi:10.1149/1.3203972

Cited by 15 publications

(4 citation statements)

References 10 publications

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“…For this work, we used high crystalline quality 200-mm optical Ge-on-Insulator (GeOI) wafers fabricated by Smart-Cut TM technology [31][32][33][34] in order to shift the mechanical failure of microbridges to higher strain. 20,31 Fig.…”

Section: Strain Induction Using Microbridge Devicesmentioning

confidence: 99%

Accurate strain measurements in highly strained Ge microbridges

Gassenq

Tardif

Guilloy

et al. 2016

Applied Physics Letters

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Ge under high strain is predicted to become a direct bandgap semiconductor. Very large deformations can be introduced using microbridge devices. However, at the microscale, strain values are commonly deduced from Raman spectroscopy using empirical linear models only established up to ε 100 =1.2% for uniaxial stress. In this work, we calibrate the Raman-strain relation at higher strain using synchrotron based microdiffraction. The Ge microbridges show unprecedented high tensile strain up to 4.9 % corresponding to an unexpected Δω=9.9 cm -1 Raman shift. We demonstrate experimentally and theoretically that the Raman strain relation is not linear and we provide a more accurate expression.

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Section: Strain Induction Using Microbridge Devicesmentioning

confidence: 99%

Accurate strain measurements in highly strained Ge microbridges

Gassenq

Tardif

Guilloy

et al. 2016

Applied Physics Letters

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“…We used the SmartCut TM process [12] to transfer the 65 nm Ge layer (capped by 2 nm of Si), compressively strained thanks to an epitaxy on a Si 0.15 Ge 0.85 VS, on top of an oxidized Si substrate. Thereafter, we were left with the following stack (from top to bottom): 40 nm of c-Ge/2 nm thick Si layer/ 140 nm thick buried SiO 2 layer/Si substrate.…”

Section: Structural Propertiesmentioning

confidence: 99%

“…In both cases, the current I OFF is quite important due to bulk leakage. The top part of thick Ge layers on Si can also be peeled off from their hosts and bonded onto oxidized Si substrates (via the SmartCut TM process), resulting in germanium-oninsulator (GeOI) substrates [12] without bulk leakage anymore [3][4][5]. The electrical defects at the Ge/buried oxide (BOX) interface (which degrade the minority carrier lifetime and create a parasitic channel for the holes) can be suppressed by Si passivation of the Ge surface prior to bonding [5].…”

Section: Introductionmentioning

confidence: 99%

Fabrication, structural and electrical properties of compressively strained Ge-on-insulator substrates

Hartmann¹,

Sanchez²,

Daele³

et al. 2010

Semicond. Sci. Technol.

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Compressively strained germanium-on-insulator (c-GeOI) substrates with a definitely reduced defect density are expected to yield superior hole mobilities together with low off-state currents in p-type metal oxide semiconductor field effect transistors (MOSFETs). In order to fabricate c-GeOI wafers, we started with double-side polished Si(0 0 1) substrates and grew, by reduced pressure-chemical vapour deposition, Si 0.15 Ge 0.85 virtual substrates (VS) on the front side. The wafer curvature was compensated thanks to the deposition of a thick Ge layer on the backside. We then grew, after a chemical mechanical polishing, various thickness (37-148 nm) Ge layers. They stayed smooth (root-mean-square roughness <5 Å) and pseudomorphically strained on the VS underneath (perpendicular lattice parameter: 5.681 Å ⇔ bulk Ge lattice parameter: 5.658 Å) up to a 74 nm thickness. These c-Ge layers were then bonded on oxidized Si substrates using the SmartCut TM process. The resulting c-GeOI substrates were of high crystalline quality, compressively strained and smooth. The threading dislocations density (8 × 10 5 cm −2 ⇔ 1.7 × 10 5 cm −2 for the SiGe VS template used to strain the c-Ge layers) was indeed 20 times less than the one associated with conventional GeOI substrates obtained from thick Ge epilayers. Pseudo-MOSFET measurements were performed to quantify the hole mobility gain in those c-GeOI substrates. A +150% enhancement compared to conventional silicon-on-insulator substrates was evidenced, validating the interest of these stacks.

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“…3,5 High hole mobilities can be achieved in devices built on thin SiGe layers on top of biaxially strained, on relaxed/strained SGOI with a high Ge fraction or even better strained /unstrained GOI substrates. 6,7 In general, strain in individual layers is generated by growth on the appropriate Si 1−x Ge x buffer layers. The amount of strain is determined by the lattice constant of the buffer layer, which depends on the Ge content.…”

mentioning

confidence: 99%

Wet Chemical Etching of Si, Si[sub 1−x]Ge[sub x], and Ge in HF:H[sub 2]O[sub 2]:CH[sub 3]COOH

Holländer

Buca

Mantl

et al. 2010

J. Electrochem. Soc.

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Device concepts are applied to strained layers ranging from pure Si to pure Ge to achieve higher carrier mobilities. Strain is generated by growth on Si1−xGex buffer layers with an appropriate Ge content. Processing of these heterostructures requires selective removal of individual layers. Different approaches to the etch Si, Si1−xGex , and Ge layers have been evaluated in terms of the etch rate, selectivity, and isotropy. All investigated etching methods used highly selective chemical etching solutions composed of HF, hydrogen peroxide, and acetic acid (HF:normalH2normalO2:CH3COOH) . The effect of the different HF content on the etch rate of pure Si, pure Ge, and Si1−xGex alloys with Ge mole fractions between 20 and 75% is presented. In general, the etch rate increases significantly with the increase in Ge content. As an example, the etch rate increases by a factor of more than 100 when the Ge content increases from 20 up to 75 atom %.

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Challenges and Progress in Germanium-on-Insulator Materials and Device Development towards ULSI Integration

Cited by 15 publications

References 10 publications

Accurate strain measurements in highly strained Ge microbridges

Accurate strain measurements in highly strained Ge microbridges

Fabrication, structural and electrical properties of compressively strained Ge-on-insulator substrates

Wet Chemical Etching of Si, Si[sub 1−x]Ge[sub x], and Ge in HF:H[sub 2]O[sub 2]:CH[sub 3]COOH

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