CGRA Tool Flow for Fast Run-Time Reconfiguration

Fricke, Florian; Werner, André; Shahin, Keyvan; Huebner, M.

doi:10.1007/978-3-319-78890-6_53

Cited by 9 publications

(3 citation statements)

References 10 publications

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“…Fricke et al present an automated toolflow that utilizes a CGRA as an overlay architecture on FPGA [5]. The authors also investigate the toolflow usability in terms of tool runtime [6].…”

Section: Related Workmentioning

confidence: 99%

UltraSynth: Insights of a CGRA Integration into a Control Engineering Environment

Wolf

Engel

Ruschke

et al. 2021

J Sign Process Syst

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Coarse Grained Reconfigurable Arrays (CGRAs) or Architectures are a concept for hardware accelerators based on the idea of distributing workload over Processing Elements. These processors exploit instruction level parallelism, while being energy efficient due to their simplistic internal structure. However, the incorporation into a complete computing system raises severe challenges at the hardware and software level. This article evaluates a CGRA integrated into a control engineering environment targeting a Xilinx Zynq System on Chip (SoC) in detail. Besides the actual application execution performance, the practicability of the configuration toolchain is validated. Challenges of the real-world integration are discussed and practical insights are highlighted.

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“…Fricke et al present an automated toolflow that utilizes a CGRA as an overlay architecture on FPGA [5]. The authors also investigate the toolflow usability in terms of tool runtime [6].…”

Section: Related Workmentioning

confidence: 99%

UltraSynth: Insights of a CGRA Integration into a Control Engineering Environment

Wolf

Engel

Ruschke

et al. 2021

J Sign Process Syst

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“…ns [30,33,71]. Furthermore, many CGRAs require customized software stacks but have inadequate tool support, since they typically involve domain-specific languages (DSLs) and custom ISAs [114].…”

Section: Contemporary Computing Platformsmentioning

confidence: 99%

Transmuter

Pal

Feng

Park

et al. 2020

Proceedings of the ACM International Conference on Parallel Architectures and Compilation Techniques

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With the end of Dennard scaling and Moore's law, it is becoming increasingly difficult to build hardware for emerging applications that meet power and performance targets, while remaining flexible and programmable for end users. This is particularly true for domains that have frequently changing algorithms and applications involving mixed sparse/dense data structures, such as those in machine learning and graph analytics. To overcome this, we present a flexible accelerator called Transmuter, in a novel effort to bridge the gap between General-Purpose Processors (GPPs) and Application-Specific Integrated Circuits (ASICs). Transmuter adapts to changing kernel characteristics, such as data reuse and control divergence, through the ability to reconfigure the on-chip memory type, resource sharing and dataflow at run-time within a short latency. This is facilitated by a fabric of lightweight cores connected to a network of reconfigurable caches and crossbars. Transmuter addresses a rapidly growing set of algorithms exhibiting dynamic data movement patterns, irregularity, and sparsity, while delivering GPU-like efficiencies for traditional dense applications. Finally, in order to support programmability and ease-of-adoption, we prototype a software stack composed of low-level runtime routines, and a high-level language library called TransPy, that cater to expert programmers and end-users, respectively. Our evaluations with Transmuter demonstrate average throughput (energy-efficiency) improvements of 5.0× (18.4×) and 4.2× (4.0×) over a high-end CPU and GPU, respectively, across a diverse set of kernels predominant in graph analytics, scientific computing and machine learning. Transmuter achieves energy-efficiency gains averaging 3.4× and 2.0× over prior FPGA and CGRA implementations of the same kernels, while remaining on average within 9.3× of state-of-the-art ASICs. CCS CONCEPTS • Computer systems organization → Reconfigurable computing; Data flow architectures; Multicore architectures.

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“…The architecture is called Virtual Coarse-Grained Reconfigurable Array (VCGRA) as it exists as an intermediate level between the accelerated algorithm and the FPGA-hardware. The structure of the architecture is presented in [FRI18]. It consists of alternating levels of processing elements and socalled virtual channels, which control the dataflow.…”

Section: Vcgra Approachmentioning

confidence: 99%

Domain Adaptive Processor Architectures

Fricke

Mahmood

Hoffmann

et al. 2020

Technologien Für Die Intelligente Automation

Self Cite

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The ongoing megatrends in industry and academia like the Internet of Things (IoT), the Industrial Internet of Things (IIoT) and Cyber-Physical Systems (CPS) present the developers of modern computer architectures with various challenges. A novel class of processors which provide more data throughput with a simultaneously tremendously reduced energy consumption are required as a backbone for these "Things". Additionally, the requirements of CPS like realtime, reliability, dependability, safety, and security are gaining in importance in these applications. This paper shows a brief overview of novel processor architectures providing high flexibility to adapt during design-and runtime to changing requirements of the application and the internal and external system status.© Der/die Herausgeber bzw. der/die Autor(en) 2020 J. Jasperneite, V. Lohweg Kommunikation und Bildverarbeitung in der Automation, (Hrsg.), Technologien für die intelligente Automation 12, https://doi.

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CGRA Tool Flow for Fast Run-Time Reconfiguration

Cited by 9 publications

References 10 publications

UltraSynth: Insights of a CGRA Integration into a Control Engineering Environment

UltraSynth: Insights of a CGRA Integration into a Control Engineering Environment

Transmuter

Domain Adaptive Processor Architectures

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