Central Processing Units for PLC implementation in Virtex-4 FPGA

Chmiel, Mirosław; Mocha, J.; Hrynkiewicz, Edward; Milik, Adam

doi:10.3182/20110828-6-it-1002.01830

Cited by 15 publications

(6 citation statements)

References 4 publications

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“…It estimates the Linkage Power by Varying Discrete Ambient Temperature .and specify which is better [1]. M.Chmeil* et.al proposed the one-bit word dual central processing unit, the purpose of this design is comparing the obtained performance with the general-purpose Microprocessor [2]. B. Pandey and Ravikant Kumar have proposed the effect of using digitally controlled impedance I/O standard in memory interface design in terms of Power consumption and also LVDCI-23 is the highest power consumer and the LVDCI-12 is the lowest one [3] Tim Tuan et.al proposed a design and implement of Pika a 90nm low FGPA core which is low power.…”

Section: Related Workmentioning

confidence: 99%

Design and Implementation of Low Power Thermal Aware Atm

Dwivedi¹

2019

GJECS

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In this Paper, we have designed a Automated Teller Machine (ATM) which is electromechanical machine works in different temperature. We analysed the Static Power at discrete temperature that is thermal scaling of ATM at XILNIX 14.1 ISE Design Suit. In this paper we have used two FGPA family one is Spartan which is Spartan 6 and another is Virtex which is Virtex 4. We have distinguished on chip power by varying the Ambient temperature from 50°C to 5°C and we observed when we lowered the temperature of both FGPA families automatically the leakage power lowered that determine our ATM are worked in any temperature without disturbing its functionality.

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Section: Related Workmentioning

confidence: 99%

Design and Implementation of Low Power Thermal Aware Atm

Dwivedi¹

2019

GJECS

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“…The same takes place upon the attempt to design a combined, Bit-Byte CPU [7]. By the foregoing reason as well as due to the fact that individual commands of the IL language must be expanded as subroutines in the C language, the list of operators in the IL language shall comprise pairs of operators capable of handling those two types of arguments, e.g.…”

Section: Influence Of the Notation Methods For An Ilmentioning

confidence: 99%

“…It can be a standard microprocessor, a dedicated microprocessor [5] or a standard microcontroller, for instance the CPU of the S7-200 PLC employs a microcontroller of MCS-51 family [6]. On the other hand, CPUs are frequently designed as multiprocessor systems that are made up of two units operating with data of bit and word formats or they incorporate a hardware coprocessor that assists execution of specific types of operations [7]. Application of FPGA units makes it possible to design dedicated microprocessor systems that are able to efficiently execute control program on the basis of a specialized microprocessor.…”

Section: Basic Ideasmentioning

confidence: 99%

About Implementation of IEC 61131-3 IL Function Blocks in Standard Microcontrollers

Chmiel¹,

Mocha²,

Hrynkiewicz³

et al. 2014

International Journal of Electronics and Telecommunications

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Abstract-The paper presents considerations on implementation of function blocks of the IL language, as fragments of control programs that use these blocks. Subsequently, the predefined function blocks of the IL language have been applied to implementation in a Central Processing Unit for a programmable controller based on standard microcontroller from such families as MCS-51, AVR and ARM with the Cortex-M3 core. The considerations refer to the IL language revision that is fully compliant with the IEC-61131-3 standards. The completed theoretical analysis demonstrated that the adopted method of the module description is really reasonable and offers substantial advantages as compared to direct calls of function modules already developed as subroutines. Also the executed experiments have proved the feasibility to arrange central units of programmable controllers on the basis of standard microcontrollers and such central units may be competitive to compact CPUs available on the market for typical PLCs.

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“…For specific implementation and evaluation purposes the FPGA devices are used. The unit is implemented as a part of the controller core [21]. The memory content difference detection is implemented without introducing any overhead in memory access (Fig.…”

Section: Hardware Assisted Event Detectionmentioning

confidence: 99%

On the systematic method of conditional control program execution by a PLC

Milik

Chmiel

Hrynkiewicz

2016

Bulletin of the Polish Academy of Sciences Technical Sciences

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Abstract. The paper presents an original idea of the selective control program execution that allows significant response time reduction. The exhaustive analysis of the PLC program performance is given. An analytic approach explains the idea of the selective control program evaluation and gives the requirements for its feasibility. There is presented a systematic and formal method of program analysis based on a data flow graph approach. The method generates acyclic graph from the control program that is subject of optimization, variable allocation and instruction generation. The graph approach allows determining variables dependencies and task partitioning required by selective program execution. The method utilize the hardware supported variable changes detection. It is transparent for system operation and enables evaluation of blocks that require update.

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Central Processing Units for PLC implementation in Virtex-4 FPGA

Cited by 15 publications

References 4 publications

Design and Implementation of Low Power Thermal Aware Atm

Design and Implementation of Low Power Thermal Aware Atm

About Implementation of IEC 61131-3 IL Function Blocks in Standard Microcontrollers

On the systematic method of conditional control program execution by a PLC

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