Cellular automata-based test pattern generators with phase shifters

A unified method for phase shifter computation

“…An example is given in Figure 1. Given a requested phase shift k for a particular stage with respect to a reference sequence, an effective technique to find which cells of the CA should be connected into an XOR gate (phase shifter) so that the resulting bit sequence is a shifted version by k positions of the reference sequence was given in Mrugalski et al [2000] based on a previous result by Ireland and Marshall [1968]. If the reference sequence is cell j of the CA, and one wants a sequence that has a phase shift of k with respect to that, then do the following: (i) initialize the CA with a vector that contains only one 1 at position j ; (ii) simulate the CA for k cycles; (iii) read off the produced vector: the positions of the 1s in it indicate the cells that should be XORed together to yield the requested sequence.…”

“…Permissions may be requested from Publications Dept., ACM, Inc., 1515 Broadway, New York, NY 10036 USA, fax: +1 (212) 869-0481, or permissions@acm.org. C 2005 ACM 1084-4309/05/0100-0157 $5.00 • D. Kagaris the designer freedom in choosing the relative phase shifts of the stages and not be bound by the inherent phase shifts of the stages of the TPG mechanism in use, networks of XOR gates, known as phase shifters, have been proposed in the literature [Bardell et al 1987;Mrugalski et al 2000;Rajski et al 1998] to be inserted between the LFSR or CA cells and the test inputs (primary inputs, test-phase inputs, and/or scan chain inputs) of the circuit under test. A phase shifter is basically a multi-input XOR gate driven by an appropriate subset of stages of the TPG mechanism in use.…”

“…The usual requirements in the phase shifter design are an upper bound B on the number of taps per phase shifter (to control the hardware overhead) and a lower bound L on the attained phase shift between successive TPG stages. Methods to obtain the appropriate subset of stages for this purpose have been given in Mrugalski et al [2000] and Rajski et al [1998], provided that the TPG in use is a Type-1 LFSR, a Type-2 LFSR, or a CA (a different algorithm is given separately for each case). In this article, we show a new, unified method that applies to any kind of LFSM.…”

Additive Cellular Automata

“…Circuit designers need "simple, regular, modular, and cascadable logic circuit structure to realize a complex function" and cellular automata, which show a significant advantage over linear feedback shift registers, the traditional circuit building block, satisfy this need (see [52] for an extensive survey). Cellular automata, in particular additive cellular automata, are of value for producing high-quality pseudorandom sequences [53,54,55,56,57]; for pseudoexhaustive and deterministic pattern generation [58,59,60,61,62,63]; for signature analysis [64,65,66]; error correcting codes [67,68]; pseudoassociative memory [69]; and cryptography [70].…”

A Hamming distance based test pattern generator with improved fault coverage

“…Though efficient methods have been developed to generate exhaustive and pseudo-exhaustive patterns [1], many large circuits require unacceptably large numbers of vectors to attain acceptable test coverage. Consequently, a number of methods have been proposed in the literature to reduce the number of required patterns with additional hardware (see [2,5,6,7,8,12,13,14] as a small sample of the numerous techniques available). In this paper, we propose a new pseudorandom test pattern generator which aims to achieve higher efficiency by using an enhanceed GLFSR [11].…”