CellSs: a Programming Model for the Cell BE Architecture

Bellens,; Perez, Josep M.; Badía, Rosa M.; Labarta, Jesús

doi:10.1109/sc.2006.17

Cited by 196 publications

(201 citation statements)

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“…Different runtime systems currently offer support for accelerators [3], or even hybrid systems. Similarly to StarPU, the Harmony runtime system targets hybrid platforms while proposing some scheduling facilities, possibly based on performance modeling [5].…”

Section: Related Workmentioning

confidence: 99%

Automatic Calibration of Performance Models on Heterogeneous Multicore Architectures

Augonnet

Thibault

Namyst

2010

Lecture Notes in Computer Science

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Abstract. Multicore architectures featuring specialized accelerators are getting an increasing amount of attention, and this success will probably influence the design of future High Performance Computing hardware. Unfortunately, programmers are actually having a hard time trying to exploit all these heterogeneous computing units efficiently, and most existing efforts simply focus on providing tools to offload some computations on available accelerators. Recently, some runtime systems have been designed that exploit the idea of scheduling -as opposed to offloading -parallel tasks over the whole set of heterogeneous computing units. Scheduling tasks over heterogeneous platforms makes it necessary to use accurate prediction models in order to assign each task to its most adequate computing unit [2]. A deep knowledge of the application is usually required to model per-task performance models, based on the algorithmic complexity of the underlying numeric kernel. We present an alternate, auto-tuning performance prediction approach based on performance history tables dynamically built during the application run. This approach does not require that the programmer provides some specific information. We show that, thanks to the use of a carefully chosen hash-function, our approach quickly achieves accurate performance estimations automatically. Our approach even outperforms regular algorithmic performance models with several linear algebra numerical kernels.

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Section: Related Workmentioning

confidence: 99%

Automatic Calibration of Performance Models on Heterogeneous Multicore Architectures

Augonnet

Thibault

Namyst

2010

Lecture Notes in Computer Science

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“…In [4] a runtime scheduling system for the IBM Cell processor which eases application partitioning among different PEs is presented. However, in that work the heterogeneous architecture is viewed in the common way where the coprocessors are responsible for executing the computationally expensive parts while the main PE is just used to control the coprocessors.…”

Section: Related Workmentioning

confidence: 99%

Predictive Runtime Code Scheduling for Heterogeneous Architectures

Jiménez

Vilanova²,

Gelado³

et al. 2009

High Performance Embedded Architectures and Compilers

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Abstract. Heterogeneous architectures are currently widespread. With the advent of easy-to-program general purpose GPUs, virtually every recent desktop computer is a heterogeneous system. Combining the CPU and the GPU brings great amounts of processing power. However, such architectures are often used in a restricted way for domain-specific applications like scientific applications and games, and they tend to be used by a single application at a time. We envision future heterogeneous computing systems where all their heterogeneous resources are continuously utilized by different applications with versioned critical parts to be able to better adapt their behavior and improve execution time, power consumption, response time and other constraints at runtime. Under such a model, adaptive scheduling becomes a critical component. In this paper, we propose a novel predictive user-level scheduler based on past performance history for heterogeneous systems. We developed several scheduling policies and present the study of their impact on system performance. We demonstrate that such scheduler allows multiple applications to fully utilize all available processing resources in CPU/GPUlike systems and consistently achieve speedups ranging from 30% to 40% compared to just using the GPU in a single application mode.

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“…Each task in S L has a property called the dependency degree, which is defined as the number of parents of the task in G. The issuer selects a task from S I and issues the task to an available processing unit, repeating issuing if idle processing units exist. Several strategies for selecting tasks have been studied [21,22]. We use a straightforward strategy where the task in S I with largest number of children is selected.…”

Section: Dynamic Partitioning and Schedulingmentioning

confidence: 99%