Cell Search in WCDMA Under Large-Frequency and Clock Errors: Algorithms to Hardware Implementation

Li, Chi-Fang; Chu, Yuan-Sun; Ho, Jan-Shin; Sheen, Wern‐Ho

doi:10.1109/tcsi.2008.916394

Cited by 10 publications

(3 citation statements)

References 13 publications

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“…Firstly, they are only valid for constant drift between the transmitter and receiver sampling clocks and secondly, they do not incorporate the multipath channel effects while evaluating the estimator's performance. An algorithm based on Sample Point Reordering (SPR) is proposed in [9] but it assumes sampling clock inaccuracies of up to only 12 ppm and the performance is affected if the amount of frequency offset present in the received signal is large. The algorithms given in [6]- [9] provide SCO estimate only and do not explain the method of proper SCO compensation for high data rate systems.…”

Section: Related Workmentioning

confidence: 99%

“…An algorithm based on Sample Point Reordering (SPR) is proposed in [9] but it assumes sampling clock inaccuracies of up to only 12 ppm and the performance is affected if the amount of frequency offset present in the received signal is large. The algorithms given in [6]- [9] provide SCO estimate only and do not explain the method of proper SCO compensation for high data rate systems.…”

Section: Related Workmentioning

confidence: 99%

“…The drift caused by the sampling clocks of the radios produces sampling clock errors at the ADC before timing and frequency estimation. Due to the sampling clock errors, ADC starts to sample at an unknown uncertain rate [9]. This uncertain rate is neither synchronous to the chip rate nor its oversampled rate.…”

Section: Problem Formulationmentioning

confidence: 99%

See 2 more Smart Citations

Robust Sampling Clock Recovery Algorithm for Wideband Networking Waveform of SDR

Zeeshan

Khan²

2022

Int. j. commun. netw. inf. secur.

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A novel technique for sampling clock recovery in a wideband networking waveform of a software defined radio is proposed. Sampling clock recovery is very important in wideband networking radio operation as it directly affects the Medium Access adaptive time slot switching rate. The proposed Sampling clock recovery algorithm consists of three stages. In the first stage, Sampling Clock Offset (SCO) is estimated at chip level. In the second stage, the SCO estimates are post-filtered to improve the tracking performance. We present a new post-filtering method namely Steady-State State-Space Recursive Least Squares with Adaptive Memory (S4RLSWAM). For the third stage of SCO compensation, a feedforward Lagrange interpolation based algorithm is proposed. Real-time hardware results have been presented to demonstrate the effectiveness of the proposed algorithms and architecture for systems requiring high data throughput. It is shown that both the proposed algorithms achieve better performance as compared to existing algorithms.

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Section: Related Workmentioning

confidence: 99%