A (15, S) CFRS (Comma-Free Reed-Solomon) code has been devised in the 3GPP W-CDMAIFDD system (3rd generation partnership project. widehend code division multiple accesslfrequcncy division duplesing) in order to facilitate frame synchronization and code-group identification in thc cell search procedure. This paper proposes a CFRS decoder chip for fast, multi-speed decoding in this application. With this fast decoder, rralization of more sophisticated cell scarch algorithms that may bc needed in some application scenarios will become feasible. Besides. a multi-spced decoding can he implemented within the same architecture, Multi-specd decoding equips a mobile for being able lo use different algorithms in different cell scarch scenarios. The decoder achieves IOU' power dissipation with low clock rate as well as fast decoding for a cordless mobile by using a fnlding systolic architccture. Finally, the proposed CFRS decoder is realized in a 3.3-V 0.35ym CMOS technology with 2 . 2~2 . 2 4 " core area and 13,311.23-mW powcr dissipation.