Cell broadband engine interconnect and memory interface

Clark, Scott; Haselhorst, Kent; Imming, K.; Irish, John D.; Krolak, Dave; Ozguner, Tolga

doi:10.1109/hotchips.2005.7476577

Cited by 8 publications

(9 citation statements)

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“…The correlation coefficient was calculated to be 0.899. One source of difference, as highlighted by the data for CP which actually achieves a normalized IPC over 1, is likely due to compiler optimizations in ptxas which may reduce the instruction count on real hardware 7 . Overall, the data shows that applications that perform well in real GPU hardware perform well in our simulator and applications that perform poorly in real GPU hardware also perform poorly in our simulator.…”

Section: (28 Shader Cores X 8-wide Pipelines)mentioning

confidence: 99%

“…Branch divergence was highlighted by Fung et al as a major source of performance loss for multithreaded SIMD 7. We only simulate the input PTX code which, in CUDA, ptxas then assembles into a proprietary binary format that we are unable to simulate.…”

Section: Branch Divergencementioning

confidence: 99%

“…They propose using an accelerator architecture (xPU) separate from the GPU to improve performance of their benchmark suite. The Cell processor [7,38] is a hardware architecture that can function like a stream processor with appropriate software support. It consists of a controlling processor and a set of SIMD co-processors each with independent program counters and instruction memory.…”

Section: Related Workmentioning

confidence: 99%

See 2 more Smart Citations

Analyzing CUDA workloads using a detailed GPU simulator

Bakhoda

Yuan

Fung

et al. 2009

2009 IEEE International Symposium on Performance Analysis of Systems and Software

1,319

825

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Section: (28 Shader Cores X 8-wide Pipelines)mentioning

confidence: 99%

Section: Branch Divergencementioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

Analyzing CUDA workloads using a detailed GPU simulator

Bakhoda

Yuan

Fung

et al. 2009

2009 IEEE International Symposium on Performance Analysis of Systems and Software

1,319

825

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show abstract

“…The Tilera TILE-Gx processors [44] and Intel Polaris [16] are examples of real packet-switched NoC implementations with up to 100 and 80 cores, respectively. The Cell BE [9] uses a circuit-switched network to connect heterogeneous cores and a single memory controller.…”

Section: Related Workmentioning

confidence: 99%

Circuit-Switched Memory Access in Photonic Interconnection Networks for High-Performance Embedded Computing

Hendry

Robinson

Gleyzer

et al. 2010

2010 ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis

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Abstract-As advancements in CMOS technology trend toward ever increasing core counts in chip multiprocessors for high-performance embedded computing, the discrepancy between on-and off-chip communication bandwidth continues to widen due to the power and spatial constraints of electronic off-chip signaling. Silicon photonics-based communication offers many advantages over electronics for network-on-chip design, namely power consumption that is effectively agnostic to distance traveled at the chip-and board-scale, even across chip boundaries. In this work we develop a design for a photonic network-on-chip with integrated DRAM I/O interfaces and compare its performance to similar electronic solutions using a detailed network-on-chip simulation. When used in a circuit-switched network, silicon nanophotonic switches offer higher bandwidth density and low power transmission, adding up to over 10× better performance and 3-5× lower power over the baseline for projective transform, matrix multiply, and Fast Fourier Transform (FFT), all key algorithms in embedded real-time signal and image processing.

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“…The First-Generation CELL processor consists of the PPE and its L2 cache, eight SPEs [2] each with its own local memory (LS) [3], a high bandwidth internal Element Interconnect Bus (EIB) [4], two configurable non-coherent I/O interfaces, a Memory Interface Controller (MIC), and a Pervasive unit that supports extensive test, monitoring, and debug functions. The high level chip diagram is shown in figure 1 below.…”

Section: Introductionmentioning

confidence: 99%

Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor

Pham¹,

Anderson²,

Behnen³

et al. 2006

Proceedings of the 2006 Conference on Asia South Pacific Design Automation - ASP-DAC '06

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Abstract--This paper reviews the design challenges that current and future processors must face, with stringent power limits and high frequency targets, and the design methods required to overcome the above challenges and address the continuing Giga-scale system integration trend. This paper then describes the details behind the design methodology that was used to successfully implement a first-generation CELL processor -a multi-core SoC. Key features of this methodology are broad optimization with fast rule-based analysis engines using macrolevel abstraction for constraints propagation up/down the design hierarchy, coupled with accurate transistor level simulation for detailed analysis. The methodology fostered the modular design concept that is inherent to the CELL architecture, enabling a high frequency design by maximizing custom circuit content through re-use, and balanced power, frequency, and die size targets through global convergence capabilities. The design has roughly 241 million transistors implemented in 90nm SOI technology with 8 levels of copper interconnects and one local interconnect layer. The chip has been tested at various temperatures, voltages, and frequencies. Correct operation has been observed in the lab on first pass silicon at frequencies well over 4GHz.

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Cell broadband engine interconnect and memory interface

Cited by 8 publications

References 0 publications

Analyzing CUDA workloads using a detailed GPU simulator

Analyzing CUDA workloads using a detailed GPU simulator

Circuit-Switched Memory Access in Photonic Interconnection Networks for High-Performance Embedded Computing

Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor

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