Case studies of data traffic management on a high-performance computing system based on multi-DSPs and Serial RapidIO interconnect

Klilou, Abdessamad; Belkouch, Saïd; Elmaizi, Asma; Elleaume, Philippe; Gall, Phlippe Le; Bourzeix, François; Hassani, Moha M’Rabet

doi:10.1109/it4od.2016.7479324

Cited by 8 publications

(2 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…RapidIO bus is a new type of packet switching interconnection technology, which has the characteristics of high performance and less pins. It is often used as the interconnection of each module in the embedded system, supports the data transmission between chips and boards, and can also be used as the backplane interconnection of the embedded system [5] . Compared with the traditional shared parallel data bus, RapidIO bus has a higher transmission rate, a wide application direction, a higher degree of scalability, and a more flexible topology, which can reduce the complexity of the internal layout of the system, and can better complete the task of data exchange [6] .…”

Section: Introductionmentioning

confidence: 99%

Application of RapidIO technology in NetGAP

Tan,

Wang,

Duan

et al. 2023

Second International Symposium on Computer Applications and Information Systems (ISCAIS 2023)

View full text Add to dashboard Cite

According to the requirement of multi-network security isolation information exchange, a multi-network isolation netgap is conceived, and the exchange unit in the netgap is newly designed. A data exchange system based on the RapidIO bus is designed in the unit, so that the exchange unit can be externally connected to four network processing units to exchange four-way data, thus solving the problem of data exchange of multi-network isolation. The system realizes high-speed data transmission and exchange with the RapidIO interconnect devices with FPGA, and the devices are connected with a star topology through a RapidIO switch. The actual test results show that the system can realize the information exchange function between the four endpoint devices, and the system data transmission rate can up to 3.4GByte/s, which exceeds the exchange unit performance of most isolation netgaps and can meet the design requirements of multi-network isolation netgap.

show abstract

Section: Introductionmentioning

confidence: 99%

Application of RapidIO technology in NetGAP

Tan,

Wang,

Duan

et al. 2023

Second International Symposium on Computer Applications and Information Systems (ISCAIS 2023)

View full text Add to dashboard Cite

show abstract

“…A straightforward model has been used and optimized as a processing parallelization strategy. All communications, including data exchange and synchronization, between processing DSP cores goes through the inter-processor communication bus Serial RapidIO (SRIO), which we have optimized its use [16,17]. The major obtained result is a parallel efficiency of about 90%.…”

Section: Introductionmentioning

confidence: 99%

Parallel implementation of pulse compression method on a multi-core digital signal processor

Klilou

2020

IJECE

Self Cite

View full text Add to dashboard Cite

Pulse compression algorithm is widely used in radar applications. It requires a huge processing power in order to be executed in real time. Therefore, its processing must be distributed along multiple processing units. The present paper proposes a real time platform based on the multi-core digital signal processor (DSP) C6678 from Texas Instruments (TI). The objective of this paper is the optimization of the parallel implementation of pulse compression algorithm over the eight cores of the C6678 DSP. Two parallelization approaches were implemented. The first approach is based on the open multi processing (OpenMP) programming interface, which is a software interface that helps to execute different sections of a program on a multi core processor. The second approach is an optimized method that we have proposed in order to distribute the processing and to synchronize the eight cores of the C6678 DSP. The proposed method gives the best performance. Indeed, a parallel efficiency of 94% was obtained when the eight cores were activated.

show abstract