Cascade Current Mirror to Improve Linearity and Consistency in SRAM In-Memory Computing

Lin, Zhiting; Zhan, Honglan; Chen, Zhongwei; Peng, Chunyu; Wu, Xiulong; Lu, Wenjuan; Zhao, Qiang; Li, Xuan; Chen, Junning

doi:10.1109/jssc.2021.3063719

Cited by 32 publications

(14 citation statements)

References 38 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…To address these problems, Lin et al [79,80] proposed a cascode current mirror (CCM) peripheral circuit and applied it to the bottom of each BL. The CCM clamps the BL voltage and proportionally duplicates the BL current in the additional capacitor, increasing the calculation linearity.…”

Section: Linearity and Consistency Problems In The Srambased Cimmentioning

confidence: 99%

A review on SRAM-based computing in-memory: Circuits, functions, and applications

Lin¹,

Tong²,

Zhang³

et al. 2022

J. Semicond.

Self Cite

View full text Add to dashboard Cite

Artificial intelligence (AI) processes data-centric applications with minimal effort. However, it poses new challenges to system design in terms of computational speed and energy efficiency. The traditional von Neumann architecture cannot meet the requirements of heavily data-centric applications due to the separation of computation and storage. The emergence of computing in-memory (CIM) is significant in circumventing the von Neumann bottleneck. A commercialized memory architecture, static random-access memory (SRAM), is fast and robust, consumes less power, and is compatible with state-of-the-art technology. This study investigates the research progress of SRAM-based CIM technology in three levels: circuit, function, and application. It also outlines the problems, challenges, and prospects of SRAM-based CIM macros.

show abstract

Section: Linearity and Consistency Problems In The Srambased Cimmentioning

confidence: 99%

A review on SRAM-based computing in-memory: Circuits, functions, and applications

Lin¹,

Tong²,

Zhang³

et al. 2022

J. Semicond.

Self Cite

View full text Add to dashboard Cite

show abstract

“…It is critical to investigate more energy-efficient circuits and architectures to implement HPC. The potential of conventional digital circuits is running low, while analog and mixed signal-based computing circuits are promising [212]. However, analog circuits are sensitive to process variation, noise, and varying voltage/temperature, especially for accurate computing.…”

Section: Current and Future Challengesmentioning

confidence: 99%

2022 roadmap on neuromorphic devices and applications research in China

Wan¹,

Wan²,

Wu³

et al. 2022

Neuromorph. Comput. Eng.

View full text Add to dashboard Cite

The data throughput in the von Neumann architecture based computing system is limited by its separated processing and memory structure and the mismatching speed between the two units. As a result, it’s quite difficult to improve the energy efficiency in conventional computing system, especially for dealing with unstructured data. Meanwhile, artificial intelligence and robotics nowadays still behave poorly in autonomy, creativity and sociality, which has been considered as the unimaginable computational requirement for sensorimotor skills. These two plights have urged the imitation and replication of the biological systems in terms of computing, sensing, and even motoring. Hence, the so-called neuromorphic system has drawn world-wide attention in recent decade, which is aimed at addressing the aforementioned needs from the mimicking of neural system. The recent development on emerging memory devices, nanotechnologies, and materials science have provided an unprecedented opportunity for this aim. This roadmap profiles the potential trend in building neuromorphic systems from the view of Chinese scientists. The content of this roadmap will cover some core topics from multidisciplinary researchers including electronics, computer science, materials, physics, and so on. The perspectives and challenges are also discussed in partly, which may serve as the guidance for the pursuing of high energy-efficient and/or bio-realistic systems that can compute, sense, and act as our human beings. This will also give birth to some excited paradigm breakers and advanced technologies in a wide spectrum of areas.

show abstract

“…7(a) is the circuit of integrating current mirror with feedback (CMF) structure. When reading multiple row data, the current mirror can be used to keep the read current constant, thus enhancing the calculated linearity [23]. The current I CL is mirrored as I CMF by the CMF structure, and the voltage of CL does not change with current charge.…”

Section: E Operations Of Input and Outputmentioning

confidence: 99%

“…In terms of circuit-level, analog IMC meets obstacles in its development due to: (1) Limited TMR causes mismatch between the impact of external input data and internal stored data on the output. (2) The analog computation behavior is more vulnerable to transistor nonlinear effects than its digital counterpart [23]. (3) Multiple bit-lines are required to enable simultaneously for cost amortization.…”

Section: Introductionmentioning

confidence: 99%

Proposal of Analog In-Memory Computing with Magnified Tunnel Magnetoresistance Ratio and Universal STT-MRAM Cell

Cai¹,

Guo²,

Liu³

et al. 2021

Preprint

View full text Add to dashboard Cite

In-memory computing (IMC) is an effectual solution for energy-efficient artificial intelligence applications. Analog IMC amortizes the power consumption of multiple sensing amplifiers with analog-to-digital converter (ADC), and simultaneously completes the calculation of multi-line data with high parallelism degree. Based on a universal one-transistor one-magnetic tunnel junction (MTJ) spin transfer torque magnetic RAM (STT-MRAM) cell, this paper demonstrates a novel tunneling magnetoresistance (TMR) ratio magnifying method to realize analog IMC. Previous concerns include low TMR ratio and analog calculation nonlinearity are addressed using device-circuit interaction. Peripheral circuits are minimally modified to enable in-memory matrix-vector multiplication. A current mirror with feedback structure is implemented to enhance analog computing linearity and calculation accuracy. The proposed design maximumly supports 1024 2-bit input and 1-bit weight multiply-andaccumulate (MAC) computations simultaneously. The 2-bit input is represented by the width of the input (IN) pulses, while the 1-bit weight is stored in STT-MRAM and the ×7500 magnified TMR (m-TMR) ratio is obtained by latching. The proposal is simulated using 28-nm CMOS process and MTJ compact model. The integral nonlinearity is reduced by 57.6% compared with the conventional structure. 9.47-25.4 TOPS/W is realized with 2-bit input, 1-bit weight and 4-bit output convolution neural network (CNN).

show abstract

Cascade Current Mirror to Improve Linearity and Consistency in SRAM In-Memory Computing

Cited by 32 publications

References 38 publications

A review on SRAM-based computing in-memory: Circuits, functions, and applications

A review on SRAM-based computing in-memory: Circuits, functions, and applications

2022 roadmap on neuromorphic devices and applications research in China

Proposal of Analog In-Memory Computing with Magnified Tunnel Magnetoresistance Ratio and Universal STT-MRAM Cell

Contact Info

Product

Resources

About