Carrier transport in amorphous SiC/crystalline silicon heterojunctions

Abstract

Charge carrier transport in chemical vapor-deposited amorphous SiC/p-type crystalline Si heterostructures has been studied over the temperature range 80–400 K, using current–voltage (I–V), current–temperature (I–T), capacitance–voltage (C–V), and capacitance relaxation (C–t) characteristics. These heterojunctions exhibit high breakdown voltages (230 V) and a diode rectification ratio of 103 at ±0.5 V. At low temperatures (80–120 K) the a-SiC behaves like a dielectric, and the interface built-in voltage can be determined from the capacitance–voltage plot. The corresponding low forward bias current flow is limited by variable-range electron hopping conductivity at Fermi level in the a-SiC layer. At increasing temperature and forward bias voltage, an additional hole current component is found with the transport governed by a multistep tunneling hole emission process through the a-SiC/c-Si heterobarrier. At still higher forward bias voltages (>0.8 V), space-charge-limited hole conduction in the presence of traps in the a-SiC bulk limits transport.

Database‐Driven Materials Selection for Semiconductor Heterojunction Design

“…Among the HTLs listed in Table , amorphous SiC has been used for hole conduction before . For CdSe LEDs, the commonly used HTL materials WO 3 and MoO 3 are both predicted to have suitable band alignment to act as HTLs.…”

Effects of thermal annealing process on the electrical properties of p+-Si/n-SiC heterojunctions

“…3 However, the large lattice mismatch between Si and SiC has limited their intrinsic performance. 4 It is found that growth of SiC layers on Si substrates results in junctions with low breakdown voltage, and high reverse-bias current, [5][6][7] possibly due to the low-temperature growth of SiC films. One way to overcome these difficulties is direct wafer bonding which can accommodate the lattice mismatch between the bonding substrates.…”

Effects of interface state charges on the electrical properties of Si/SiC heterojunctions

“…6 In growing SiC layers on Si, 7 because of the large lattice mismatch and difference in thermal expansion coefficients between Si and SiC, a marked residual stress and defects with high densities are frequently encountered, which limits the intrinsic performance of grown Si/SiC heterojunctions. 8 One way to overcome these difficulties is direct wafer bonding such as hydrophilic wafer bonding 9 and surfaceactivated bonding (SAB). 10 In SAB, surfaces of substrates are activated by the fast atom beams of Ar prior to bonding, which enables us to bond substrates without heating them.…”