Carrier scattering induced by thickness fluctuation of silicon-on-insulator film in ultrathin-body metal–oxide–semiconductor field-effect transistors

Uchida, Ken; Takagi, Shin

doi:10.1063/1.1571227

Cited by 145 publications

(107 citation statements)

References 13 publications

Supporting

Mentioning

102

Contrasting

Order By: Relevance

“…There we employ the linearized Boltzmann formalism in NWs with flat electrostatic potential in the cross section, and consider the band edge shift as the dominant influence of the SRS. That 7 mechanism is the dominant for ultra-narrow NWs, of diameters D<8nm, and is responsible for the µ~D 6 mobility behavior observed in ultra thin-layers and NWs is [14,45]. For the diameters of interest in this new work, i.e.…”

Section: Approachmentioning

confidence: 99%

Bandstructure and mobility variations in p-type silicon nanowires under electrostatic gate field

Neophytou

Baumgärtner

Stanojević

et al. 2013

Solid-State Electronics

View full text Add to dashboard Cite

The sp 3 d 5 s * -spin-orbit-coupled atomistic tight-binding (TB) model is used for the electronic structure calculation of Si nanowires (NWs), self consistently coupled to a 2D Poisson equation, solved in the cross section of the NW. Upon convergence, the linearized Boltzmann transport theory is employed for the mobility calculation, including carrier scattering by phonons and surface roughness. As the channel is driven into inversion, for [111] and [110] NW devices of diameters D>10nm the curvature of the bandstructure increases and the hole effective mass becomes lighter, resulting in a ~50% mobility increase. Such improvement is large enough to compensate for the detrimental effect of surface roughness scattering. The effect is very similar to the bandstructure variations and mobility improvement observed under geometric confinement, however, in this case confinement is caused by electrostatic gating. We provide explanations for this behavior based on features of the heavy-hole band. This effect could be exploited in the design of p-type NW devices. We note, finally, that the "apparent" mobility of low dimensional short channel transistors is always lower than the intrinsic channel diffusive mobility due to the detrimental influence of the so called "ballistic" mobility.

show abstract

Section: Approachmentioning

confidence: 99%

Bandstructure and mobility variations in p-type silicon nanowires under electrostatic gate field

Neophytou

Baumgärtner

Stanojević

et al. 2013

Solid-State Electronics

View full text Add to dashboard Cite

show abstract

“…Note that even a roughness of the order of 1Å at interfaces affects current characteristics in advanced LSI technologies as shown in Ref. 12 Thus, the non-uniformity of solid-state qubits to collective decoherence environment is much larger and rather local compared with that of optical or NMR qubits, and it will be necessary to consider the effects of second order O(η 2 ) or higher symmetrybreaking perturbation. In this paper, we theoretically describe the effect of large non-uniformity (∼5%) of charge qubit parameters on DF states based on time-dependent density matrix (DM) equations considering the measurement process by detector current.…”

mentioning

confidence: 99%

“…|Ψ [4] 1 (1234) = 2 −1 (|01 −|10 ) (12) ⊗ (|01 −|10 ) (34) , |Ψ [4] 2 (1234) = 1/(2 √ 3)(2|0011 − |0101 − |0110 − |1001 − |1010 + 2|1100 ) (1234) ( 1) where |1001 (1234) = |1 1 |0 2 |0 3 |1 4 and so on. The DF subsystem starts from three qubits.…”

mentioning

confidence: 99%

Decoherence-free states for charge qubits under local nonuniformity

Tanamoto

Fujita

2005

Phys. Rev. B

View full text Add to dashboard Cite

We analyze the robustness of decoherence-free (DF) subspace and subsystem in charge qubits, when difference from the collective decoherence measurement condition is large (∼5%) in the long time period, which is applicable for solid-state qubits using as a quantum memory. We solve master equations of up to four charge qubits and a detector as a quantum point contact (QPC). We show that robustness of DF states is strongly affected by local non-uniformities. We also discuss the possible two-qubit logical states by exactly solving the master equations.

show abstract

“…Low I OFF and steep S result in a high I ON / I OFF ratio. 5 The high I ON / I OFF ratio will enable the transistors to be used to design integrated electronics on arbitrary substrates for the applications, where low power and fast access times are demanded.However, when the nc-Si layer becomes very thin, even the smallest thickness variation can result in highly random potential fluctuations due to the strong quantum confinement effect along the channel thickness direction, 6 and charge traps at grain boundaries ͑GBs͒ will also deplete the nc-Si grains of free carriers. 7 These will make the carrier transport from the source to the drain through the device channel become much more complicated, and result in electrical characteristics that may not be described by conventional fieldeffect transistor ͑FET͒ models.…”

mentioning

confidence: 99%

Current percolation in ultrathin channel nanocrystalline silicon transistors

Guo

Silva

Ishii

2008

Applied Physics Letters

View full text Add to dashboard Cite

The ultrathin channel nanocrystalline silicon transistor shows greatly improved switching performance and has demonstrated its candidacy for low power applications. In this work, by careful observation of the current-voltage and threshold voltage characteristics, we find that current percolation occurs when the channel is thinner than 3.0 nm due to strong quantum confinement induced large potential variations over the channel. We show that the device channel width must be at least 0.3 m to avoid percolative "pinch off" for 0.5 m channel length devices. Theoretical analysis performed on the devices agrees well with the experimental data and provides important guidelines to model and optimize the devices for circuit design. © 2008 American Institute of Physics. ͓DOI: 10.1063/1.2965807͔There has been significant interest in silicon nanostructures for electronics, photovoltaic, and optoelectronic applications, including zero-dimensional silicon nanocrystallites, one-dimensional ͑1D͒ quantum wires, and two-dimensional ͑2D͒ thin layers. 1-3 All these structures are designed to use the quantum confinement effect to enhance the device's performance. To design transistors for integrated electronics, however, the ideal structure must also be compatible with conventional silicon device processing. The 2D silicon layers appear to be the best choice for current fabrication techniques due to the planar geometry that is utilized in current complementary metal oxide semiconductor technology. Recently, by controlling the deposition ͑chemical vapor deposition͒ process at a very low deposition rate, ultrathin ͑Ͻ5 nm͒ flat nanocrystalline silicon ͑nc-Si͒ layers were achieved and applied as the channel for transistors in low power applications. 4 It is proven that using such an ultrathin channel effectively improves the switching performance of thinfilm transistors in nc-Si. 5 When the channel becomes thinner, the OFF-state leakage current I OFF decreases significantly, which is attributed to the stronger quantum confinement effect along the channel thickness direction. The subthreshold swing ͑S͒ also becomes steeper because the effect of gate voltage on the channel surface potential increases. Low I OFF and steep S result in a high I ON / I OFF ratio. 5 The high I ON / I OFF ratio will enable the transistors to be used to design integrated electronics on arbitrary substrates for the applications, where low power and fast access times are demanded.However, when the nc-Si layer becomes very thin, even the smallest thickness variation can result in highly random potential fluctuations due to the strong quantum confinement effect along the channel thickness direction, 6 and charge traps at grain boundaries ͑GBs͒ will also deplete the nc-Si grains of free carriers. 7 These will make the carrier transport from the source to the drain through the device channel become much more complicated, and result in electrical characteristics that may not be described by conventional fieldeffect transistor ͑FET͒ models. In the present study, current ...

show abstract

Carrier scattering induced by thickness fluctuation of silicon-on-insulator film in ultrathin-body metal–oxide–semiconductor field-effect transistors

Cited by 145 publications

References 13 publications

Bandstructure and mobility variations in p-type silicon nanowires under electrostatic gate field

Bandstructure and mobility variations in p-type silicon nanowires under electrostatic gate field

Decoherence-free states for charge qubits under local nonuniformity

Current percolation in ultrathin channel nanocrystalline silicon transistors

Contact Info

Product

Resources

About