Cardinality Counting Circuit for Real-Time Abnormal Traffic Detection

Sannomiya, Shuji; Sato, Akira; Yoshida, Kenichi; Nishikawa, Hiroaki

doi:10.1109/compsac.2017.81

Cited by 3 publications

(1 citation statement)

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“…Although Refs. [2], [3] reports basic ideas, this paper confirms the adequacy of those ideas by providing experimental results; these are described in Section 4. The remainder of this paper is organized as follows.…”

Section: Introductionsupporting

confidence: 61%

Abnormal Traffic Detection Circuit with Real-time Cardinality Counter

Sannomiya

Sato

Yoshida

et al. 2018

Journal of Information Processing

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To identify abnormal traffic such as P2P flows, DDoS attacks, and Internet worms, this paper discusses a circuit design to realize real-time abnormal traffic detection in broadband networks. Real-time counting of cardinality is the key feature of the circuit. Although our previous study showed that cardinality counting is effective for detecting various types of abnormal traffic, the slowness of DRAM access prevented us from deploying cardinality counting in backbone networks. To address the problem of DRAM access time, this paper proposes a new algorithm for cardinality counting. By changing the order of the cardinality counting process, the proposed algorithm enables parallel accesses of DRAM circuits, which hides the slow DRAM access time through a pipeline circuit. In addition, we propose a new hashing function that also hides the DRAM access problem. It partially replaces scattered addresses with successive addresses, in order to use a faster DRAM burst access. We also report the accuracy of the cardinality counting of the new algorithm, and describe the estimated processing performance based on a pipeline tact level circuit simulation. Our experimental results show that the use of the self-timed pipeline circuit can help realize cardinality counting at rates up to 100 Gbps.

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Section: Introductionsupporting

confidence: 61%