Carbon Nano Tube Field Effect Transistors Based Ternary Ex-OR and Ex-NOR Gates

Patcha, Kavitha; Musala, Sarada; Vijayavardhan, K.; Vani, Y. Sudha; Srinivasulu, Avireni

doi:10.2174/1573413712666151216221629

Cited by 22 publications

(6 citation statements)

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“…In Real-Time Fault-Tolerant Full Adder design approach the number of hardware components is high due to redundancy in design and thus are more costly [32]- [33]. Due to the redundant circuit design, critical path delay is increased and thereby increases the overall circuit delay [34]- [38].…”

Section: Existing Fault-tolerant Circuit Designs Approachmentioning

confidence: 99%

A Full Adder Design with CNFETs for Real Time, Fault Tolerant and Mission Critical Applications

Srinivasulu¹,

Saini²,

Kumawat³

2020

ELS

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The VLSI based circuits often pose challenges in the form of various faults (such as transient faults, permanent faults, stuck-at-faults). These faults appear even after testing also. They occur because of reduction in the size of the circuit or during realtime implementation, as these faults are difficult to detect. It is very important to detect and rectify all such faults to make the system foolproof and achieve expected functionality. In this paper, 12 transistors based, full adder circuit (12T-FAC) using Carbon Nanotube Field Effect Transistor (CNFET) technology is proposed. The proposed design based on CNFET provides high fault resistance towards transient, permanent faults and works with least power, delay and power-delay product (PDP). Later, features like fault detection and correction circuit have been added in 12T-FAC. The final version of full adder circuit capable of correcting errors has been used in designing applications like multipliers. The proposed full adder circuit was designed with CNFET technology, simulated at 32 nm with supply voltage +0.9 V using the Cadence Virtuoso CAD tool. The model used is Stanford PTM.

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Section: Existing Fault-tolerant Circuit Designs Approachmentioning

confidence: 99%

A Full Adder Design with CNFETs for Real Time, Fault Tolerant and Mission Critical Applications

Srinivasulu¹,

Saini²,

Kumawat³

2020

ELS

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“…The CNTFET's mathematical relation for threshold voltage is determined by (1) Vth≃Ebg/2e ≃ 0.436/Dcnt (nm) (1) where Ebg is the energy band gap of carbon nano-tube, e is the charge of electron and Dcnt is the diameter of the carbon nano-tube. It can be seen from (1) that the threshold voltage of a CNTFET is inversely related to the diameter of its nano-tubes, which is computed by (2) 0.0783…”

Section: Heavily Doped Cnt Segments For Source/drainmentioning

confidence: 99%

“…This research was performed in the Microelectronics Laboratory of BITS Pilani, K. K. Birla Goa Campus, India. performance elevated compact circuits [1][2][3]. These challenges could be overcome by introducing the recently developed CMOS nano-devices viz CNTFET, Quantum Dot Cellular Automation (QCA) and also Single Electron Technology (SET), which are believed to be able to replace conventional CMOS technology [4] in the near future.…”

Section: Introductionmentioning

confidence: 99%

An Operational Transconductance Amplifiers Based Sinusoidal Oscillator Using CNTFETs

Bhargav

Srinivasulu

Pal

2018

2018 International Conference on Applied Electronics (AE)

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1 Abstract-A new sinusoidal oscillator using Carbon Nanotube Field Effect Transistors (CNTFET) based Operational Transconductance Amplifiers (CNOTA) with grounded capacitors is presented in this paper. The proposed current-mode oscillator thus implemented and having grounded capacitor feature, fulfils the need for realizations of systems used in combination with various other systems/ subsystems -both voltage-mode and current mode. It also ensures simplicity in implementation by using a single-ended CNOTA. The analytical model is given for the circuit leading to fulfilment of the condition of oscillation at tuned frequency. The proposed sinusoidal oscillator is primarily used in the field of signal dispensation applications, telecommunication networks, communication-equipment and control modules. The benefits derived from the introduced model are validated by simulation carried out at a supply voltage of ±1.8 V in Cadence virtuoso using spectre model libraries. They are further tested with the aid of 32 nm model of Carbon Nanotube Field Effect Transistor (CNTFET) technology obtained through open source. The proposed design (and the model provided) is found to be in good agreement with the obtained results.

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“…Currently, CNTFETs and GNRFETs are drawing wide attention of researchers due to their extensive electrical mechanical properties. CNTFET and GNRFET based ternary logic systems have been reported in literature, [9][10][11][12][13] where implemented different logic levels have been realized using tuning the threshold voltages. However, one of the major challenge is in fabrication where it becomes very difficult to design different CNTFET based logic gates.…”

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confidence: 99%

Signal Integrity Assessment of GNRFET-Based Ternary Logic for Multi Layered GNR Interconnects with Dielectric Insertion

Kumar¹,

Malothu²,

Agrawal

et al. 2023

ECS J. Solid State Sci. Technol.

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Signal integrity assessment was carried out for graphene nanoribbon field-effect transistor (GNRFET)-based ternary logic with dielectric inserted multi-layered GNR (MLGNR) interconnects. The analyses were carried out for crosstalk effects and eye diagrams with and without shielding lines. First, it was observed that the dielectric inserted MLGNR interconnects show better than copper (Cu) and multiwall carbon nanotube (MWCNT) interconnects. Then, an active shield technique was adopted, and it was observed that the transistor exhibits better performance than without shield and passive shield techniques. Also, the power-delay product performance parameter was evaluated and showed that the active shield technique outperforms passive technique. Further, the eye diagram analysis was carried out for different bit rates. The different performance analyses were carried out for 10 nm technology node.

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Carbon Nano Tube Field Effect Transistors Based Ternary Ex-OR and Ex-NOR Gates

Cited by 22 publications

References 0 publications

A Full Adder Design with CNFETs for Real Time, Fault Tolerant and Mission Critical Applications

A Full Adder Design with CNFETs for Real Time, Fault Tolerant and Mission Critical Applications

An Operational Transconductance Amplifiers Based Sinusoidal Oscillator Using CNTFETs

Signal Integrity Assessment of GNRFET-Based Ternary Logic for Multi Layered GNR Interconnects with Dielectric Insertion

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