Carbon-Based Liner for RESET Current Reduction in Self-Heating Phase- Change Memory Cells

Thermal Confinement by Monolayer MoS2 for Reduced RESET Current in Phase Change Memory Pillar Cells

“…Figure 2 shows the simulated melting current for simple pillar cells of height h = 50 nm and pillar cells with a C-liner of h = 30 and 50 nm for widths ranging between 55 and 80 nm, which matches reasonably well with the experimental data. For the remainder of this study, we have kept the height of the GST layer 30 nm, in line with the device fabricated by De Proft et al 15 Next, we investigate the effects of the melting current after incorporating the TiO 2 layer and MoS 2 monolayer in pillar cells. In Device-2 (3 nm TiO 2 layer on BE), a low resistance filament must be formed to enable memory operations.…”

“…The latter can be achieved either by using phase change materials with higher thermal resistance or by incorporating a thermally resistive interfacial layer between the PCM and the electrodes. 12−14 Some reported interfacial materials offering excellent thermal confinement include carbon-based liners, 15 MoS 2 , 16 Bi 2 Te 3 , 17 graphene, 14 fullerene, 18 and GeN. 19 Yang et al employed a conductive bridge switching technique to achieve programming energy as low as a few femtojoules. 20 A recent work by Neumann et al 16 has demonstrated the use of a two-dimensional molybdenum disulfide (MoS 2 ) monolayer as an excellent material for confining heat at the interface of the GST and the bottom electrode.…”

“…32 Although the use of 2D materials as interfacial materials has shown considerable success in confining heat at the GST/electrode interface, studies have been mostly limited to mushroom cell geometries. Only very recently, Proft et al 15 used a carbon-based liner between the GST layer and the top electrode, resulting in a 60% reduction in the melting (RESET) current. However, the use of a MoS 2 layer in pillar cell geometry is yet to be reported.…”

“…Figure2. Simulation model validation by comparing the simulated melting currents with the experimental results 15. …”

Robust Simulations of Nanoscale Phase Change Memory: Dynamics and Retention

“…Thermal boundary resistance (TBR) at the interface between different materials, for example, the interface of GST/BE, is easily incorporated into the simulation. It facilitates a confinement of heating and hence the reduction of the reset current, which may be intentionally introduced in the PCM cell design [21,22]. Figure 1b briefly shows the discretization with cuboidal grids.…”