Capping Layers to Improve the Electrical Stress Stability of MoS₂ Transistors

Abstract

Two-dimensional (2D) materials offer exciting possibilities for numerous applications, including next-generation sensors and field-effect transistors (FETs). With their atomically thin form factor, it is evident that molecular activity at the interfaces of 2D materials can shape their electronic properties. Although much attention has focused on engineering the contact and dielectric interfaces in 2D material-based transistors to boost their drive current, less is understood about how to tune these interfaces to improve the long-term stability of devices. In this work, we evaluated molybdenum disulfide (MoS 2 ) transistors under continuous electrical stress for periods lasting up to several days. During stress in ambient air, we observed temporary threshold voltage shifts that increased at higher gate voltages or longer stress durations, correlating to changes in interface trap states (ΔN it ) of up to 10 12 cm −2 . By modifying the device to include either SU-8 or Al 2 O 3 as an additional dielectric capping layer on top of the MoS 2 channel, we were able to effectively reduce or even eliminate this unstable behavior. However, we found this encapsulating material must be selected carefully, as certain choices actually amplified instability or compromised device yield, as was the case for Al 2 O 3 , which reduced yield by 20% versus all other capping layers. Further refining these strategies to preserve stability in 2D devices will be crucial for their continued integration into future technologies.

Are 2D Interfaces Really Flat?

“…Meanwhile, among the seven devices in the array, only one device presented in Figure functions normally after the hBN stacking and ALD process steps. This low yield could be related to the annealing effect of the ALD process at 120 °C . Hence, statistical representation of the performance increase also warrants future studies.…”

“…Producing a high-quality gate dielectric and interface on 2D materials remains a major challenge for fabricating highperformance FETs and large-scale integrated circuits due to uneven nucleation and thickness scaling. 5 AlO x grown by using atomic layer deposition (ALD) is a commonly used encapsulation dielectric 27 and has been shown to exhibit a doping effect for MoS 2 FETs. 28 The flatness of the interface between amorphous 3D high-k dielectrics and 2D interfaces has profound implications for studying strain, defects, trapped charges, and their impact on device performance.…”

“…This low yield could be related to the annealing effect of the ALD process at 120 °C. 27 Hence, statistical representation of the performance increase also warrants future studies.…”

“…As covered in ref , MoS 2 was grown using chemical vapor deposition at 750 °C for 10 min under a flow of argon gas at a rate of 100 sccm at ambient pressure. The MoS 2 film was then transferred onto AlO x (grown by ALD at 120 °C) on a p++ Si substrate to reduce the substrate coupling compared to MoS 2 on as-grown substrate . Sixteen nm of Ni contacts were then fabricated onto the MoS 2 using e-beam lithography and e-beam evaporation.…”

Understanding and Mapping Sensitivity in MoS2 Field-Effect-Transistor-Based Sensors

“…These and other similar measurement methods have seen some use on 2D-FETs previously . While EFM and KPFM are available with many traditional AFM instruments, our modified SGM approach required additional channels of synchronized measurements provided by a custom in situ FET characterization system (Synch-Dev), portions of which have been described previously. , This latter approach provided the most illuminating and pertinent data, enabling direct correlation between the SGM tip position and the charge with the MoS 2 FET behavior under active bias. Many reports have presented SGM on graphene devices, − mostly from the perspectives of observing insights stemming from graphene’s band structure.…”