2017
DOI: 10.1109/tcsii.2016.2628965
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Capless LDO Regulator Achieving −76 dB PSR and 96.3 fs FOM

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Cited by 46 publications
(27 citation statements)
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“…The power board has four different output voltages (+10, −10, +5, and −5V), which are used for preamplifiers and the programable gain amplifier (PGA). Another separate +5V power supply for the digital potentiometer on the analog board and the DAC7714 chip and 3.3 V power provide digital logic power for the analog-to-digital converter AD7767 (Yun et al, 2017). The power diagram is shown in Fig.…”
Section: High-precision Linear Power Circuitmentioning
confidence: 99%
“…The power board has four different output voltages (+10, −10, +5, and −5V), which are used for preamplifiers and the programable gain amplifier (PGA). Another separate +5V power supply for the digital potentiometer on the analog board and the DAC7714 chip and 3.3 V power provide digital logic power for the analog-to-digital converter AD7767 (Yun et al, 2017). The power diagram is shown in Fig.…”
Section: High-precision Linear Power Circuitmentioning
confidence: 99%
“…Also, the design complexity of a DC-DC converter is much higher than that of a linear regulator. The use of a linear regulator for power management affords design simplicity, less silicon area, low cost, and no ripple [5][6][7][8][9][10][11][12].…”
Section: Introductionmentioning
confidence: 99%
“…In the proposed LDO, the reference voltage is externally generated. This work [40] (JSSC 2010) [46] (VLSI Table 3.2, save at 1MHz where the LDOs [45,50] reported slightly higher PSRR (only at the 1MHz point) but at lower heavy Iload (50mA vs 100mA in the proposed LDO). Of particular interest, the proposed LDO is the only design that achieves >60dB PSRR throughout the 10MHz frequency range and for 100mA load current range.…”
Section: Psrr Measurementsmentioning
confidence: 74%
“…In contrast, the PSRR of state-of-the-art LDOs are high only over a limited loading current range (≤50mA) and/or limited frequency range. The highest loading current (100mA) of the proposed LDO is more than ×2 larger and the lowest loading current (100µA) is an order of magnitude lower than the reported designs [40,45,46,50]. Put simply, the proposed LDO features the highest PSRR for 3-orders of magnitude change in the loading current (100µA to 100mA) whilst the reported competing LDOs suffer lower PSRR despite having a substantially lower loading current range of less than 2-orders of magnitude.…”
Section: Psrr Measurementsmentioning
confidence: 82%
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