Capacitor-coupled logic using GaAs depletion-mode f.e.t.s

Mellor, P.J.T.; Livingstone, A.W.

doi:10.1049/el:19800532

Cited by 12 publications

(1 citation statement)

References 2 publications

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“…Early logic families were based on a combination of diodes and normally ON devices (Depletion-mode FETs). Buffered FET Logic (BFL) [11], Schoktty Diodes FET Logic (SDFL) [12], and CapacitiveCoupled FET Logic (CCFL) [13] represent a few examples. These families however exhibit some drawbacks, such as large area occupation and power consumption regarding the BFL, fan-out capability regarding the SDFL, and finally low operating frequency issues regarding the CCFL.…”

Section: Potential Gaas Logic Familiesmentioning

confidence: 99%

Design and Realization of GaAs Digital Circuit for Mixed Signal MMIC Implementation in AESA Applications

Bentini

Pasciuto

Ciccognani

et al. 2011

International Journal of Microwave Science and Technology

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A complete design flow starting from the technological process development up to the fabrication of digital circuits is presented. The aim of this work is to demonstrate the GaAs Enhancement/Depletion (E/D) double stop-etch technology implementation feasibility for digital applications, aimed at mixed signal circuit integration. On the basis of the characterization of small E/D devices with different Gate peripheries, developed by the SELEX-SI foundry, and the analysis of several GaAs-based logical families, the most suitable logic for the available technology has been selected. Then, simple test vehicles (level shifters, NOR logic gates and D Flip-Flops) have been designed, realized, and measured to validate the design strategy applied to the GaAs E/D process. These logical circuits are preliminary to the design of a more complex serial-to-parallel converter, to be implemented onto the same chip together with RF analog blocks, such as stepped attenuators and phase shifters.

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Section: Potential Gaas Logic Familiesmentioning

confidence: 99%