Capacitance–voltage study of single-crystalline Si dots on ultrathin buried SiO2 formed by nanometer-scale local oxidation

Ishikawa, Yasuhiko; Kosugi, Masaaki; Kumezawa, Minoru; Tsuchiya, Toshiaki; Tabe, Michiharu

doi:10.1016/s0040-6090(00)00837-3

Cited by 17 publications

(5 citation statements)

References 16 publications

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“…16 ͒ Ac-a͒ Author to whom correspondence should be addressed; electronic mail: y-ishikawa@rie.shizuoka.ac.jp cording to our previous studies, 11,13,14 the present condition should result in the lateral size of the SiN islands of 10-20 nm, the thickness of only about 0.5 nm, and the density of about 3ϫ10 11 cm Ϫ2 . After heating the sample at 930°C for the surface oxide desorption, N 2 molecules of 1 ϫ10 Ϫ5 Torr were supplied at 750°C for 100 s to form ultrasmall SiN islands ͓Fig.…”

Section: A Fabrication Of Samplessupporting

confidence: 69%

Effect of nanometer-scale corrugation on densities of gap states and fixed charges at the thermally grown SiO2/Si interface

Ishikawa

Kosugi

Tabe

2001

Journal of Applied Physics

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A study of the relationship between Si/SiO 2 between interface charges and roughnessEffect of nanometer-scale corrugation on gap state and fixed charge densities at the SiO 2 /Si interface in Si ͑001͒ metal-oxide-semiconductor ͑MOS͒ capacitors has been studied by capacitance-voltage (C -V) and conductance-voltage (G/ -V) measurements. As the interface corrugation, a high density of Si protrusions, composed of a microscopic ͑001͒ plane at the top and high-index planes ͓typically ͑115͒ planes͔ at the sides, were formed by a microscopic selective oxidation technique developed by the authors. By changing the selective oxidation condition, the area ratio of the top and side planes was varied. As a result, it was found that each of C -V and G/ -V curves showed a mixture of two curves with different flatband voltages. This reflects that the interface fixed charge density at the side high-index planes is larger than that at the top ͑001͒ plane, similar to previous reports for classical MOS capacitors with a macroscopic flat interface. Furthermore, it was found that the side high-index interface has a higher gap state density than the top ͑001͒, also similar to the previous macroscopic results. Such orientation dependence of gap state and fixed charge densities in the nanometer regime will play a significant role in electrical properties of ultrasmall Si devices, which accompany a relatively large area of curved interfaces.

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Section: A Fabrication Of Samplessupporting

confidence: 69%

Effect of nanometer-scale corrugation on densities of gap states and fixed charges at the thermally grown SiO2/Si interface

Ishikawa

Kosugi

Tabe

2001

Journal of Applied Physics

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“…This type of frequency dispersion of the accumulation capacitance has been observed by other groups in Si implanted Si-SiO 2 structures 24,25 and in Si NCs embedded within an insulator matrix. 26 It should be mentioned that high resistivity elec-trode effects may also lead to the appearance of similar frequency dispersion phenomena. Their main influence takes place at high frequencies and at the accumulation regime.…”

Section: B Admittance Measurementsmentioning

confidence: 99%

“…26 The physical mechanism by which the carriers are transferred in and out of the Si-NCs is the trap-assisted tunneling as in the case of the I-V measurements although the physical conditions monitored in each case are different. In the I-V measurements, the transient peak is the result of charge injection from the substrate to the NC layer, while in the case of admittance measurements the charge exchange occurs with charged Si-NCs and involves charge trapping sites around the quasi-Fermi level.…”

Section: B Admittance Measurementsmentioning

confidence: 99%

Dynamic charge transfer effects in two-dimensional silicon nanocrystal layers embedded within SiO2

Ioannou‐Sougleridis

Nassiopoulou

2009

Journal of Applied Physics

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In this work, we study two distinct electrical behaviors, which are often observed in Si nanocrystal memory gate stacks: the transient peak of the current-voltage characteristics and the frequency dependence of the admittance characteristics at strong accumulation. These effects are manifestations of a high electrical transparency tunnel oxide in conjunction with a good quality control oxide. The high electrical transparency tunnel oxide results from hydrogen-related defects that are formed within it during the high temperature processing steps and promotes the electrical communication between the silicon substrate and the silicon nanocrystal layer at low electric fields, while no significant charge transfer is observed at low voltages between the silicon nanocrystals and the gate electrode. These conditions favor the electrical charging/discharging of the silicon nanocrystal layer via the trap-assisted tunneling mechanism and to the appearance of electrostatic screening effects. These dynamic phenomena appear either as a displacement current peak at the onset of accumulation or as frequency dependent admittance characteristics at strong accumulation.

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“…in 6(a) 9 and correlate with the interface gap states located at the interface between gate oxide and nc-Si dots, and consequently result in a shoulder capacitance. 10 However, for the annealed sample, the interface gap states of nc-Si dots have been reduced and then three capacitance peaks instead of the shoulder of capacitance can be clearly observed. Under this condition, only unoccupied ground states and excited states in nc-Si dots can respond to electron tunneling events, which is shown in Fig.…”

Section: Resultsmentioning

confidence: 97%

New Nanocrystalline si Floating Gate Structue for Nonvolatile Memory Application

Shi

Chen

et al. 2002

MRS Proc.

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We report a direct experiment evidence for holes and electrons charging in a new nanocrystalline Si (nc-Si) floating gate structure (SiO 2 /nc-Si/SiO 2 /c-Si) fabricated in-situ by plasma oxidation and layer by layer deposition technique in a plasma enhanced chemical vapor deposition (PECVD) system. In this nc-Si floating gate structures, the thickness of tunneling SiO 2 layer is about 2 nm and the mean grain size of nc-Si is 6 nm obtained from Raman scattering and AFM measurements. The discrete quantum level and Coulomb charging energy for a single electron have been observed in large ensemble of nc-Si dots by frequency dependent capacitance spectroscopy, which demonstrates that the Coulomb blockade for electron in nc-Si dots is larger than size fluctuation effects on the quantum confinement for our nc-Si floating gate structure. Quantitatively, the experiment results of capacitance spectroscopy are in good agreement with the theoretical calculations. By contrasted with silicon single electron transistor memory made by using ultra fancy nanotechnology, nc-Si based memory can be fabricated with a minimum perturbation of conventional silicon technology and may be closest to industrial application.

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Capacitance–voltage study of single-crystalline Si dots on ultrathin buried SiO2 formed by nanometer-scale local oxidation

Cited by 17 publications

References 16 publications

Effect of nanometer-scale corrugation on densities of gap states and fixed charges at the thermally grown SiO2/Si interface

Effect of nanometer-scale corrugation on densities of gap states and fixed charges at the thermally grown SiO2/Si interface

Dynamic charge transfer effects in two-dimensional silicon nanocrystal layers embedded within SiO2

New Nanocrystalline si Floating Gate Structue for Nonvolatile Memory Application

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