Capacitance extraction method for a gate-induced quantum dot in silicon nanowire metal–oxide–semiconductor field-effect transistors

Abstract

An improved method of extracting the coupling capacitances of quantum dot structure is reported. This method is based on measuring the charge transfer current in the silicon nanowire metal-oxide-semiconductor field-effect transistor (MOSFET), in which the channel closing and opening are controlled by applying alternating-current biases with a half period phase shift to the dual lower gates. The capacitances around the dot, including fringing capacitances and barrier capacitances, are obtained by analyzing the relation between the transfer current and the applied voltage. This technique could be used to extract the capacitance parameters not only from the bulk silicon devices, but also from the silicon-oninsulator (SOI) MOSFETs.

Comparison of Strain Effect between Aluminum and Palladium Gated MOS Quantum Dot Systems

“…As the SiO 2 thickness increases, the overall strain reduces significantly shifting the unintentional dots from x = −40 and +40 to x = −30 and +30. However, it is important to note that thicker SiO 2 may require larger voltages across all the metallic gates and may eventually cause leakage currents between the gate to gate layer [26]. Next, the Figure 1b model is studied using the same method.…”

A Design Method to Improve Temperature Uniformity on Wafer for Rapid Thermal Processing

“…Step 4 Next, the power of tungsten-halogen lamps required at a given annealing temperature is estimated based on the geometrical parameters of the lamp array obtained from the optimization procedure. First, the relative irradiance density is calculated by substituting the geometric parameters, h = 64, R = (0,32,63,96,128), and N = (1,6,12,23,45), into Equations (3) and (4). Then, under the ambient temperature setting, T 0 , the power of tungsten-halogen lamp can be obtained according to Equation (1).…”

“…Then, under the ambient temperature setting, T0, the power of tungsten-halogen lamp can be obtained according to Equation (1). Here, the term 2ε1σT0 4 in Equation (1) originates from the thermal energy of the quartz underlay and the heat of the gas inside the chamber, which can be determined by measurement. Figure 5 shows the relationship between the power of tungsten-halogen lamp and the annealing temperature of silicon wafer at T0 = 300, 400, 500, 600, 700, and 800 K. The influence of ambient temperature on the power of tungsten-halogen lamp is relatively small, as evident from Figure 5.…”

“…The continuing downscaling of design features in ultra-large-scale integration (ULSI) is leading to manufacturing challenges in the semiconductor fabrication technology [1][2][3][4]. Hence, there is a need for better control of process parameters in order to meet the increasing demand.…”