Capability Models for Manycore Memory Systems: A Case-Study with Xeon Phi KNL

Optimizations of Unstructured Aerodynamics Computations for Many-core Architectures

“…Figure 5 shows our optimized flux routine performance with respect to the choice of the KNL configuration modes. Our results align with the findings of [46], in which a KNL performance model is developed to micro-benchmark the implications of varying the clustering/memory modes. They show nearly negligible influence on performance of cluster and memory mode combinations, except for SNC-4, where there is a small perceptible degradation in the runtime.…”

“…Thus far, SNC modes are experimental modes [41]. Therefore, application code performance on SNC modes is highly unpredictable and, thereby, very hard to justify it [46]. Nonetheless, to further ensure that SNC mode specifically does not have an influence on the performance of our application, we enable SNC on Skylake [47], and we experiment the code there.…”

“…13. Strong thread scaling of the gradient kernel 77 GB/s for the DRAM and 314 GB/s for the MCDRAM, whereas the STREAM write benchmark is about 36 GB/s for the DRAM and 171 GB/s for the MCDRAM [46]. At best, we achieve roughly 25% out of the STREAM read/write performance for the DRAM, and about 17% for the MCDRAM.…”

“…Their model is recently extended to explore KNL [46], which includes constructing several performance models for certain combinations of KNL clustering and memory modes. Furthermore, the work of [76] performs several experimentations on KNL with different applications, through which Roofline performance models are drawn for different configurations of KNL.…”

“…Some of this work is inherited and customized to our application code. For instance, SoA of [68], AoSoA of [22], low-level, MCDRAM-aware allocator of [39], data dependency conflicts migration of [71], Hilbert-based recursive tiling/blocking of [74], cache line aware optimization of [1], [46], [75], and partial coloring of [79]. In our work, we deal with irregular memory access patterns through optimizing for the cache line awareness based upon minimizing memory reference arithmetic and pointer chasing, as well as localizing a large bulk of computations inside a compute core.…”