CAP: Color-aware task partitioning for multicore real-time applications

Gracioli, Giovani; Fröhlich, Antônio Augusto

doi:10.1109/etfa.2014.7005118

Cited by 3 publications

(14 citation statements)

References 13 publications

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“…Our system model is similar to our previous work [1]. We consider a system with a multicore processor with m identical processors (cores) running at a fixed clock speed.…”

Section: System Modelmentioning

confidence: 99%

“…Modern multicore processors hide latency by implementing mechanisms around shared resources [1]. Complex techniques, such as FIFOs, prefetchers and caches, impact the estimation of the worst-case execution time (WCET) during the schedulability analysis [1,2]. The shared cache levels (L2 and/or L3) are one of the main factors that affect the predictability in multicore processors [2][3][4] because memory accesses in one core may interfere with the cache of another core, delaying the execution times of the affected tasks, for instance.…”

Section: Introductionmentioning

confidence: 99%

“…Cache partitioning through the use of page colouring is the most common and successful approach because it increases the system predictability [1][2][3][4][5][6]. However, when cooperating tasks interact with each other by sharing colours (true or false sharing), 'the cache coherence protocol implemented in hardware invalidates shared cache lines whenever they are written and this may lead to deadline misses' [1]. In fact, a recent study has shown an increase of up to 15 times on the observed WCET when tasks share cache colours [6].…”

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

“…Recent works have been proposed to deal with shared caches and to ease the WCET estimation in multicore processors. Cache partitioning through the use of page colouring is the most common and successful approach because it increases the system predictability [1–6]. However, when cooperating tasks interact with each other by sharing colours (true or false sharing), ‘the cache coherence protocol implemented in hardware invalidates shared cache lines whenever they are written and this may lead to deadline misses’ [1].…”

Section: Introductionmentioning

confidence: 99%

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Two‐phase colour‐aware multicore real‐time scheduler

Gracioli

Fröhlich

2017

IET Computers & Digital Techniques

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A two-phase colour-aware real-time scheduler to reduce the contention caused by the cache coherence protocol due to accesses to shared cache partitions in a multicore processor is proposed. The first phase is a colour-aware task partitioning (CAP) algorithm that assigns tasks that share colours to a common processor whenever possible. The second phase is a dynamic colour-aware scheduler that detects cache coherence activities at run-time, preventing the execution of tasks that interfere with each other and thus reducing the contention caused by the cache coherence protocol. The authors compare the proposed scheduler with a CAP without run-time optimisation and with the best-fit decreasing heuristic in terms of deadline misses and tardiness of several task sets using a real-time operating system and a modern 8-core processor. The results indicate that the proposed scheduler improves deadline tardiness and provides hard real-time guarantees by combining cache and task partitioning with scheduling optimisations.

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“…Our system model is similar to our previous work [1]. We consider a system with a multicore processor with m identical processors (cores) running at a fixed clock speed.…”

Section: System Modelmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Two‐phase colour‐aware multicore real‐time scheduler

Gracioli

Fröhlich

2017

IET Computers & Digital Techniques

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Performance Monitoring Features in EPOS

Horstmann

Hoffmann

Fröhlich

2021

2021 XI Brazilian Symposium on Computing Systems Engineering (SBESC)

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An Evolutionary Approach for the Hierarchical Scheduling of Safety- and Security-Critical Multicore Architectures

2020

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The aerospace and defense industry is facing an end-of-life production issue with legacy embedded uniprocessor systems. Most, if not all, embedded processor manufacturers have already moved towards system-on-a-chip multicore architectures. Current scheduling arrangements do not consider schedules related to safety and security. The methods are also inefficient because they arbitrarily assign larger-than-necessary windows of execution. This research creates a hierarchical scheduling framework as a model for real-time multicore systems to integrate the scheduling for safe and secure systems. This provides a more efficient approach which automates the migration of embedded systems’ real-time software tasks to multicore architectures. A novel genetic algorithm with a unique objective function and encoding scheme was created and compared to classical bin-packing algorithms. The simulation results show the genetic algorithm had 1.8–2.5 times less error (a 56–71% difference), outperforming its counterparts in uniformity in utilization. This research provides an efficient, automated method for commercial, private and defense industries to use a genetic algorithm to create a feasible two-level hierarchical schedule for real-time embedded multicore systems that address safety and security constraints.

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CAP: Color-aware task partitioning for multicore real-time applications

Cited by 3 publications

References 13 publications

Two‐phase colour‐aware multicore real‐time scheduler

Two‐phase colour‐aware multicore real‐time scheduler

Performance Monitoring Features in EPOS

An Evolutionary Approach for the Hierarchical Scheduling of Safety- and Security-Critical Multicore Architectures

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