Calculation of the current response of the spatially modulated light CMOS detector

Abstract

We present an analytical model that allows to calculate the current response of a spatially modulated light CMOS detector (SML-detector) and compare this response with the response of a traditional CMOS photodetector. It is shown that the SML detector already yields a three orders of magnitude faster response time than a traditional CMOS detector in a 0.25 m CMOS technology. This response time will further decrease as CMOS technology evolves. This analytical expression is compared with a numerical solution of the diffusion equation and with experimental results. Both show an excellent correspondence. Therefore we can conclude that the SML-detector is the solution of choice for cheap, CMOS-compatible receivers in integrated opto-electronic systems.Index Terms-CMOS analog integrated circuits, optical receivers, photodetectors.

Fabrication of a low-cost module for gigabit ethernet transceivers

“…This type of detector results in a large bandwidth, because the difference of the directly measured light and the referred version of the detected light are measured [4]. In this way, the effect of the slow diffusion is compensated by measuring a differential signal.…”

“…In this product, a CMOS-integrated detector is used [4]. This allows a large degree of integration: the detector can be directly integrated in the receiver electronics.…”

3Gb/s monolithically integrated photodiode and pre-amplifier in standard 0.18μm CMOS

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For cost, size, and assembly reasons monolithically integrated CMOS optical detectors are preferred in (very) short-range optical data communication [1,2] and in optical storage systems [3]. Another advantage of an integrated photodiode is that high interconnect capacitances and inductances are avoided.

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“…This effect typically forms the speed bottleneck in integrated CMOS optical receivers. One solution [1,2] achieves 700Mb/s by cancelling the effect of the slowly diffusing carriers by subtracting two diode responses; this, however, results in lower responsivity and hence lower sensitivity. A solution is described for high-speed data communication with integrated photodiodes without reducing circuit responsivity, achieving 3Gb/s datarate by exploiting an analog equalizer.…”

“…The total noise in the circuit is dominated by the TIA (~75%), while the equalizer's frequency response is band-limited to maximize the SNR [4]. Then, with approximately 60% more photocurrent available in comparison with [1,2], for the same SNR more than four times higher data-rates are achieved. With respect to conventional CMOS detectors a few orders higher data-rates are achieved.…”